Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
Aaron Durbin | 2c4aab3 | 2015-03-06 23:26:06 -0600 | [diff] [blame] | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame^] | 16 | #include <cpu/intel/car/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 18 | #include <soc/iosf.h> |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame^] | 19 | #include <soc/iomap.h> |
| 20 | #include <soc/gpio.h> |
| 21 | #include <soc/lpc.h> |
| 22 | #include <soc/spi.h> |
| 23 | #include <soc/pmc.h> |
Aaron Durbin | ba170b47 | 2013-09-23 14:15:42 -0500 | [diff] [blame] | 24 | |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 25 | static void setup_mmconfig(void) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 26 | { |
| 27 | uint32_t reg; |
| 28 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 29 | /* Set up the MMCONF range. The register lives in the BUNIT. The |
| 30 | * IO variant of the config access needs to be used initially to |
| 31 | * properly configure as the IOSF access registers live in PCI |
| 32 | * config space. */ |
| 33 | reg = 0; |
| 34 | /* Clear the extended register. */ |
| 35 | pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); |
| 36 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; |
| 37 | pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); |
| 38 | reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | |
| 39 | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; |
| 40 | pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); |
| 41 | } |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 42 | |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame^] | 43 | static void program_base_addresses(void) |
| 44 | { |
| 45 | uint32_t reg; |
| 46 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 47 | |
| 48 | /* Memory Mapped IO registers. */ |
| 49 | reg = PMC_BASE_ADDRESS | 2; |
| 50 | pci_write_config32(lpc_dev, PBASE, reg); |
| 51 | reg = IO_BASE_ADDRESS | 2; |
| 52 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 53 | reg = ILB_BASE_ADDRESS | 2; |
| 54 | pci_write_config32(lpc_dev, IBASE, reg); |
| 55 | reg = SPI_BASE_ADDRESS | 2; |
| 56 | pci_write_config32(lpc_dev, SBASE, reg); |
| 57 | reg = MPHY_BASE_ADDRESS | 2; |
| 58 | pci_write_config32(lpc_dev, MPBASE, reg); |
| 59 | reg = PUNIT_BASE_ADDRESS | 2; |
| 60 | pci_write_config32(lpc_dev, PUBASE, reg); |
| 61 | reg = RCBA_BASE_ADDRESS | 1; |
| 62 | pci_write_config32(lpc_dev, RCBA, reg); |
| 63 | |
| 64 | /* IO Port Registers. */ |
| 65 | reg = ACPI_BASE_ADDRESS | 2; |
| 66 | pci_write_config32(lpc_dev, ABASE, reg); |
| 67 | reg = GPIO_BASE_ADDRESS | 2; |
| 68 | pci_write_config32(lpc_dev, GBASE, reg); |
| 69 | } |
| 70 | |
| 71 | static void spi_init(void) |
| 72 | { |
| 73 | u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); |
| 74 | u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); |
| 75 | uint32_t reg; |
| 76 | |
| 77 | /* Disable generating SMI when setting WPD bit. */ |
| 78 | write32(scs, read32(scs) & ~SMIWPEN); |
| 79 | /* |
| 80 | * Enable caching and prefetching in the SPI controller. Disable |
| 81 | * the SMM-only BIOS write and set WPD bit. |
| 82 | */ |
| 83 | reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; |
| 84 | reg &= ~EISS; |
| 85 | write32(bcr, reg); |
| 86 | } |
| 87 | |
| 88 | static void tco_disable(void) |
| 89 | { |
| 90 | uint32_t reg; |
| 91 | |
| 92 | reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); |
| 93 | reg |= TCO_TMR_HALT; |
| 94 | outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); |
| 95 | } |
| 96 | |
| 97 | static void byt_config_com1_and_enable(void) |
| 98 | { |
| 99 | uint32_t reg; |
| 100 | |
| 101 | /* Enable the UART hardware for COM1. */ |
| 102 | reg = 1; |
| 103 | pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); |
| 104 | |
| 105 | /* Set up the pads to select the UART function */ |
| 106 | score_select_func(UART_RXD_PAD, 1); |
| 107 | score_select_func(UART_TXD_PAD, 1); |
| 108 | } |
| 109 | |
| 110 | /* The distinction between nb/sb/cpu is not applicable here so |
| 111 | just pick the one that is called first. */ |
| 112 | void bootblock_early_northbridge_init(void) |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 113 | { |
| 114 | /* Allow memory-mapped PCI config access. */ |
| 115 | setup_mmconfig(); |
| 116 | |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame^] | 117 | program_base_addresses(); |
| 118 | |
| 119 | tco_disable(); |
| 120 | |
| 121 | if (CONFIG(ENABLE_BUILTIN_COM1)) |
| 122 | byt_config_com1_and_enable(); |
| 123 | |
| 124 | spi_init(); |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 125 | } |