Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
Aaron Durbin | 2c4aab3 | 2015-03-06 23:26:06 -0600 | [diff] [blame] | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
Aaron Durbin | ba170b47 | 2013-09-23 14:15:42 -0500 | [diff] [blame] | 21 | #include <cpu/x86/cache.h> |
| 22 | #include <cpu/x86/msr.h> |
| 23 | #include <cpu/x86/mtrr.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame^] | 24 | #include <soc/iosf.h> |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 25 | #include <cpu/intel/microcode/microcode.c> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 26 | |
Aaron Durbin | ba170b47 | 2013-09-23 14:15:42 -0500 | [diff] [blame] | 27 | static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) |
| 28 | { |
| 29 | msr_t basem, maskm; |
| 30 | basem.lo = base | type; |
| 31 | basem.hi = 0; |
| 32 | wrmsr(MTRRphysBase_MSR(reg), basem); |
| 33 | maskm.lo = ~(size - 1) | MTRRphysMaskValid; |
| 34 | maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; |
| 35 | wrmsr(MTRRphysMask_MSR(reg), maskm); |
| 36 | } |
| 37 | |
| 38 | static void enable_rom_caching(void) |
| 39 | { |
| 40 | msr_t msr; |
| 41 | |
| 42 | disable_cache(); |
| 43 | /* Why only top 4MiB ? */ |
| 44 | set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); |
| 45 | enable_cache(); |
| 46 | |
| 47 | /* Enable Variable MTRRs */ |
| 48 | msr.hi = 0x00000000; |
| 49 | msr.lo = 0x00000800; |
| 50 | wrmsr(MTRRdefType_MSR, msr); |
| 51 | } |
| 52 | |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 53 | static void setup_mmconfig(void) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 54 | { |
| 55 | uint32_t reg; |
| 56 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 57 | /* Set up the MMCONF range. The register lives in the BUNIT. The |
| 58 | * IO variant of the config access needs to be used initially to |
| 59 | * properly configure as the IOSF access registers live in PCI |
| 60 | * config space. */ |
| 61 | reg = 0; |
| 62 | /* Clear the extended register. */ |
| 63 | pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); |
| 64 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; |
| 65 | pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); |
| 66 | reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | |
| 67 | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; |
| 68 | pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); |
| 69 | } |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 70 | |
| 71 | static void bootblock_cpu_init(void) |
| 72 | { |
| 73 | /* Allow memory-mapped PCI config access. */ |
| 74 | setup_mmconfig(); |
| 75 | |
| 76 | /* Load microcode before any caching. */ |
| 77 | intel_update_microcode_from_cbfs(); |
| 78 | enable_rom_caching(); |
| 79 | } |