Blame - src/cpu/x86/Kconfig - coreboot

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Stefan Reinauer	9d5e36e	2015-04-27 13:40:16 -0700	[diff] [blame]	1	config PARALLEL_MP
Kyösti Mälkki	41a2c73	2021-05-29 21:23:18 +0300	[diff] [blame]	2	def_bool y
				3	depends on !LEGACY_SMP_INIT
				4	depends on SMP
Stefan Reinauer	9d5e36e	2015-04-27 13:40:16 -0700	[diff] [blame]	5	help
				6	This option uses common MP infrastructure for bringing up APs
				7	in parallel. It additionally provides a more flexible mechanism
				8	for sequencing the steps of bringing up the APs.
				9
Aaron Durbin	b21e362	2016-12-07 00:32:19 -0600	[diff] [blame]	10	config PARALLEL_MP_AP_WORK
				11	def_bool n
				12	depends on PARALLEL_MP
				13	help
				14	Allow APs to do other work after initialization instead of going
				15	to sleep.
Stefan Reinauer	9d5e36e	2015-04-27 13:40:16 -0700	[diff] [blame]	16
Kyösti Mälkki	41a2c73	2021-05-29 21:23:18 +0300	[diff] [blame]	17	config LEGACY_SMP_INIT
				18	bool
				19
Patrick Georgi	0e9a925	2009-10-06 20:48:07 +0000	[diff] [blame]	20	config UDELAY_LAPIC
				21	bool
				22	default n
				23
Aaron Durbin	fd8291c	2013-04-29 17:18:49 -0500	[diff] [blame]	24	config LAPIC_MONOTONIC_TIMER
				25	def_bool n
				26	depends on UDELAY_LAPIC
Aaron Durbin	fd8291c	2013-04-29 17:18:49 -0500	[diff] [blame]	27	help
Elyes HAOUAS	d6e9686	2016-08-21 10:12:15 +0200	[diff] [blame]	28	Expose monotonic time using the local APIC.
Aaron Durbin	fd8291c	2013-04-29 17:18:49 -0500	[diff] [blame]	29
Patrick Georgi	e135ac5	2012-11-20 11:53:47 +0100	[diff] [blame]	30	config UDELAY_LAPIC_FIXED_FSB
				31	int
				32
Ronald G. Minnich	669c4a9	2009-08-29 03:00:51 +0000	[diff] [blame]	33	config UDELAY_TSC
				34	bool
				35	default n
				36
Kyösti Mälkki	0d6ddf8	2019-10-31 14:52:20 +0200	[diff] [blame]	37	config UNKNOWN_TSC_RATE
				38	bool
				39	default y if LAPIC_MONOTONIC_TIMER
Aaron Durbin	8e73b5d	2013-05-01 15:27:09 -0500	[diff] [blame]	40
Aaron Durbin	e850164	2013-04-29 22:22:55 -0500	[diff] [blame]	41	config TSC_MONOTONIC_TIMER
				42	def_bool n
				43	depends on UDELAY_TSC
Aaron Durbin	e850164	2013-04-29 22:22:55 -0500	[diff] [blame]	44	help
				45	Expose monotonic time using the TSC.
				46
Stefan Reinauer	0db6820	2012-08-07 14:44:51 -0700	[diff] [blame]	47	config TSC_SYNC_LFENCE
				48	bool
				49	default n
				50	help
				51	The CPU driver should select this if the CPU needs
				52	to execute an lfence instruction in order to synchronize
				53	rdtsc. This is true for all modern AMD CPUs.
				54
				55	config TSC_SYNC_MFENCE
				56	bool
				57	default n
				58	help
				59	The CPU driver should select this if the CPU needs
				60	to execute an mfence instruction in order to synchronize
				61	rdtsc. This is true for all modern Intel CPUs.
				62
Arthur Heymans	47be2d9	2019-10-12 17:32:09 +0200	[diff] [blame]	63	config SETUP_XIP_CACHE
				64	bool
Arthur Heymans	47be2d9	2019-10-12 17:32:09 +0200	[diff] [blame]	65	depends on !NO_XIP_EARLY_STAGES
				66	help
				67	Select this option to set up an MTRR to cache XIP stages loaded
				68	from the bootblock. This is useful on platforms lacking a
				69	non-eviction mode and therefore need to be careful to avoid
				70	eviction.
				71
Stefan Reinauer	8aedcbc	2010-12-16 23:37:17 +0000	[diff] [blame]	72	config CPU_ADDR_BITS
				73	int
				74	default 36
				75
				76	config LOGICAL_CPUS
				77	bool
				78	default y
				79
Kyösti Mälkki	4d372c7	2019-07-08 13:48:57 +0300	[diff] [blame]	80	config HAVE_SMI_HANDLER
				81	bool
				82	default n
				83	depends on (SMM_ASEG \|\| SMM_TSEG)
				84
Kyösti Mälkki	8abf66e	2019-07-08 09:56:00 +0300	[diff] [blame]	85	config NO_SMM
Kyösti Mälkki	4d372c7	2019-07-08 13:48:57 +0300	[diff] [blame]	86	bool
				87	default n
				88
Kyösti Mälkki	8abf66e	2019-07-08 09:56:00 +0300	[diff] [blame]	89	config SMM_ASEG
Duncan Laurie	8bb7723	2012-01-09 22:11:25 -0800	[diff] [blame]	90	bool
				91	default n
Kyösti Mälkki	8abf66e	2019-07-08 09:56:00 +0300	[diff] [blame]	92	depends on !NO_SMM
				93
				94	config SMM_TSEG
				95	bool
				96	default y
				97	depends on !(NO_SMM \|\| SMM_ASEG)
				98
				99	if SMM_TSEG
Aaron Durbin	50a3464	2013-01-03 17:38:47 -0600	[diff] [blame]	100
				101	config SMM_MODULE_HEAP_SIZE
				102	hex
				103	default 0x4000
Aaron Durbin	50a3464	2013-01-03 17:38:47 -0600	[diff] [blame]	104	help
				105	This option determines the size of the heap within the SMM handler
				106	modules.
Aaron Durbin	57686f8	2013-03-20 15:50:59 -0500	[diff] [blame]	107
Raul E Rangel	d3b8393	2018-06-12 10:43:09 -0600	[diff] [blame]	108	config SMM_MODULE_STACK_SIZE
				109	hex
				110	default 0x400
Raul E Rangel	d3b8393	2018-06-12 10:43:09 -0600	[diff] [blame]	111	help
				112	This option determines the size of the stack within the SMM handler
				113	modules.
				114
Marshall Dawson	46fc6847	2018-10-25 13:01:55 -0600	[diff] [blame]	115	config SMM_STUB_STACK_SIZE
				116	hex
				117	default 0x400
Marshall Dawson	46fc6847	2018-10-25 13:01:55 -0600	[diff] [blame]	118	help
				119	This option determines the size of the stack within the SMM handler
				120	modules.
				121
Kyösti Mälkki	8abf66e	2019-07-08 09:56:00 +0300	[diff] [blame]	122	endif
				123
Patrick Georgi	ce2564a	2015-09-05 20:21:24 +0200	[diff] [blame]	124	config SMM_LAPIC_REMAP_MITIGATION
				125	bool
				126	default y if NORTHBRIDGE_INTEL_I945
				127	default y if NORTHBRIDGE_INTEL_GM45
Angel Pons	95de231	2020-02-17 13:08:53 +0100	[diff] [blame]	128	default y if NORTHBRIDGE_INTEL_IRONLAKE
Patrick Georgi	ce2564a	2015-09-05 20:21:24 +0200	[diff] [blame]	129	default n
				130
Damien Zammit	149c4c5	2015-11-28 21:27:05 +1100	[diff] [blame]	131	config SERIALIZED_SMM_INITIALIZATION
				132	bool
				133	default n
				134	help
				135	On some CPUs, there is a race condition in SMM.
				136	This can occur when both hyperthreads change SMM state
				137	variables in parallel without coordination.
				138	Setting this option serializes the SMM initialization
				139	to avoid an ugly hang in the boot process at the cost
				140	of a slightly longer boot time.
				141
Aaron Durbin	57686f8	2013-03-20 15:50:59 -0500	[diff] [blame]	142	config X86_AMD_FIXED_MTRRS
				143	bool
				144	default n
				145	help
				146	This option informs the MTRR code to use the RdMem and WrMem fields
				147	in the fixed MTRR MSRs.
Aaron Durbin	e0785c0	2013-10-21 12:15:29 -0500	[diff] [blame]	148
Marshall Dawson	98f43a1	2019-08-05 16:18:56 -0600	[diff] [blame]	149	config X86_AMD_INIT_SIPI
				150	bool
				151	default n
				152	help
				153	This option limits the number of SIPI signals sent during during the
				154	common AP setup. Intel documentation specifies an INIT SIPI SIPI
				155	sequence, however this doesn't work on some AMD platforms.
				156
Lee Leahy	ae738ac	2016-07-24 08:03:37 -0700	[diff] [blame]	157	config SOC_SETS_MSRS
				158	bool
				159	default n
				160	help
				161	The SoC requires different access methods for reading and writing
				162	the MSRs. Use SoC specific routines to handle the MSR access.
Tim Wawrzynczak	6fcc46d	2021-04-19 13:47:36 -0600	[diff] [blame]	163
				164	config RESERVE_MTRRS_FOR_OS
				165	bool
				166	default n
				167	help
				168	This option allows a platform to reserve 2 MTRRs for the OS usage.
				169	The Intel SDM documents that the the first 6 MTRRs are intended for
				170	the system BIOS and the last 2 are to be reserved for OS usage.
				171	However, modern OSes use PAT to control cacheability instead of
				172	using MTRRs.