Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 3 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
| 4 | * Copyright (C) 2011 Stefan Tauner |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 5 | * Copyright (C) 2018 Siemens AG |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 6 | * |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but without any warranty; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | /* This file is derived from the flashrom project. */ |
| 19 | #include <stdint.h> |
| 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 22 | #include <bootstate.h> |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 23 | #include <commonlib/helpers.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 24 | #include <delay.h> |
| 25 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 26 | #include <device/pci_ops.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 27 | #include <console/console.h> |
Kyösti Mälkki | 7ba1440 | 2019-02-07 12:44:00 +0200 | [diff] [blame] | 28 | #include <device/device.h> |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 29 | #include <device/pci.h> |
| 30 | #include <spi_flash.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 31 | |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 32 | #include <spi-generic.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 33 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 34 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 35 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 36 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 37 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 38 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 39 | static int spi_is_multichip(void); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 40 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 41 | typedef struct spi_slave ich_spi_slave; |
| 42 | |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 43 | static int g_ichspi_lock = 0; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 44 | |
| 45 | typedef struct ich7_spi_regs { |
| 46 | uint16_t spis; |
| 47 | uint16_t spic; |
| 48 | uint32_t spia; |
| 49 | uint64_t spid[8]; |
| 50 | uint64_t _pad; |
| 51 | uint32_t bbar; |
| 52 | uint16_t preop; |
| 53 | uint16_t optype; |
| 54 | uint8_t opmenu[8]; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 55 | uint32_t pbr[3]; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 56 | } __packed ich7_spi_regs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 57 | |
| 58 | typedef struct ich9_spi_regs { |
| 59 | uint32_t bfpr; |
| 60 | uint16_t hsfs; |
| 61 | uint16_t hsfc; |
| 62 | uint32_t faddr; |
| 63 | uint32_t _reserved0; |
| 64 | uint32_t fdata[16]; |
| 65 | uint32_t frap; |
| 66 | uint32_t freg[5]; |
| 67 | uint32_t _reserved1[3]; |
| 68 | uint32_t pr[5]; |
| 69 | uint32_t _reserved2[2]; |
| 70 | uint8_t ssfs; |
| 71 | uint8_t ssfc[3]; |
| 72 | uint16_t preop; |
| 73 | uint16_t optype; |
| 74 | uint8_t opmenu[8]; |
| 75 | uint32_t bbar; |
| 76 | uint8_t _reserved3[12]; |
| 77 | uint32_t fdoc; |
| 78 | uint32_t fdod; |
| 79 | uint8_t _reserved4[8]; |
| 80 | uint32_t afc; |
| 81 | uint32_t lvscc; |
| 82 | uint32_t uvscc; |
| 83 | uint8_t _reserved5[4]; |
| 84 | uint32_t fpb; |
| 85 | uint8_t _reserved6[28]; |
| 86 | uint32_t srdl; |
| 87 | uint32_t srdc; |
| 88 | uint32_t srd; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 89 | } __packed ich9_spi_regs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 90 | |
| 91 | typedef struct ich_spi_controller { |
| 92 | int locked; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 93 | uint32_t flmap0; |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 94 | uint32_t flcomp; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 95 | uint32_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 96 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 97 | ich9_spi_regs *ich9_spi; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 98 | uint8_t *opmenu; |
| 99 | int menubytes; |
| 100 | uint16_t *preop; |
| 101 | uint16_t *optype; |
| 102 | uint32_t *addr; |
| 103 | uint8_t *data; |
| 104 | unsigned databytes; |
| 105 | uint8_t *status; |
| 106 | uint16_t *control; |
| 107 | uint32_t *bbar; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 108 | uint32_t *fpr; |
| 109 | uint8_t fpr_max; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 110 | } ich_spi_controller; |
| 111 | |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 112 | static ich_spi_controller g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 113 | |
| 114 | enum { |
| 115 | SPIS_SCIP = 0x0001, |
| 116 | SPIS_GRANT = 0x0002, |
| 117 | SPIS_CDS = 0x0004, |
| 118 | SPIS_FCERR = 0x0008, |
| 119 | SSFS_AEL = 0x0010, |
| 120 | SPIS_LOCK = 0x8000, |
| 121 | SPIS_RESERVED_MASK = 0x7ff0, |
| 122 | SSFS_RESERVED_MASK = 0x7fe2 |
| 123 | }; |
| 124 | |
| 125 | enum { |
| 126 | SPIC_SCGO = 0x000002, |
| 127 | SPIC_ACS = 0x000004, |
| 128 | SPIC_SPOP = 0x000008, |
| 129 | SPIC_DBC = 0x003f00, |
| 130 | SPIC_DS = 0x004000, |
| 131 | SPIC_SME = 0x008000, |
| 132 | SSFC_SCF_MASK = 0x070000, |
| 133 | SSFC_RESERVED = 0xf80000 |
| 134 | }; |
| 135 | |
| 136 | enum { |
| 137 | HSFS_FDONE = 0x0001, |
| 138 | HSFS_FCERR = 0x0002, |
| 139 | HSFS_AEL = 0x0004, |
| 140 | HSFS_BERASE_MASK = 0x0018, |
| 141 | HSFS_BERASE_SHIFT = 3, |
| 142 | HSFS_SCIP = 0x0020, |
| 143 | HSFS_FDOPSS = 0x2000, |
| 144 | HSFS_FDV = 0x4000, |
| 145 | HSFS_FLOCKDN = 0x8000 |
| 146 | }; |
| 147 | |
| 148 | enum { |
| 149 | HSFC_FGO = 0x0001, |
| 150 | HSFC_FCYCLE_MASK = 0x0006, |
| 151 | HSFC_FCYCLE_SHIFT = 1, |
| 152 | HSFC_FDBC_MASK = 0x3f00, |
| 153 | HSFC_FDBC_SHIFT = 8, |
| 154 | HSFC_FSMIE = 0x8000 |
| 155 | }; |
| 156 | |
| 157 | enum { |
| 158 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 159 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 160 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 161 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 162 | }; |
| 163 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 164 | #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 165 | |
| 166 | static u8 readb_(const void *addr) |
| 167 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 168 | u8 v = read8(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 169 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 170 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
| 171 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 172 | return v; |
| 173 | } |
| 174 | |
| 175 | static u16 readw_(const void *addr) |
| 176 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 177 | u16 v = read16(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 178 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 179 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
| 180 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 181 | return v; |
| 182 | } |
| 183 | |
| 184 | static u32 readl_(const void *addr) |
| 185 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 186 | u32 v = read32(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 187 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 188 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
| 189 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 190 | return v; |
| 191 | } |
| 192 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 193 | static void writeb_(u8 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 194 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 195 | write8(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 196 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
| 197 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 198 | } |
| 199 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 200 | static void writew_(u16 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 201 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 202 | write16(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 203 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
| 204 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 205 | } |
| 206 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 207 | static void writel_(u32 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 208 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 209 | write32(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 210 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
| 211 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 212 | } |
| 213 | |
| 214 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 215 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 216 | #define readb_(a) read8(a) |
| 217 | #define readw_(a) read16(a) |
| 218 | #define readl_(a) read32(a) |
| 219 | #define writeb_(val, addr) write8(addr, val) |
| 220 | #define writew_(val, addr) write16(addr, val) |
| 221 | #define writel_(val, addr) write32(addr, val) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 222 | |
| 223 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 224 | |
| 225 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 226 | { |
| 227 | const uint8_t *bvalue = value; |
| 228 | uint8_t *bdest = dest; |
| 229 | |
| 230 | while (size >= 4) { |
| 231 | writel_(*(const uint32_t *)bvalue, bdest); |
| 232 | bdest += 4; bvalue += 4; size -= 4; |
| 233 | } |
| 234 | while (size) { |
| 235 | writeb_(*bvalue, bdest); |
| 236 | bdest++; bvalue++; size--; |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | static void read_reg(const void *src, void *value, uint32_t size) |
| 241 | { |
| 242 | const uint8_t *bsrc = src; |
| 243 | uint8_t *bvalue = value; |
| 244 | |
| 245 | while (size >= 4) { |
| 246 | *(uint32_t *)bvalue = readl_(bsrc); |
| 247 | bsrc += 4; bvalue += 4; size -= 4; |
| 248 | } |
| 249 | while (size) { |
| 250 | *bvalue = readb_(bsrc); |
| 251 | bsrc++; bvalue++; size--; |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | static void ich_set_bbar(uint32_t minaddr) |
| 256 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 257 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 258 | const uint32_t bbar_mask = 0x00ffff00; |
| 259 | uint32_t ichspi_bbar; |
| 260 | |
| 261 | minaddr &= bbar_mask; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 262 | ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 263 | ichspi_bbar |= minaddr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 264 | writel_(ichspi_bbar, cntlr->bbar); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 265 | } |
| 266 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 267 | void spi_init(void) |
| 268 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 269 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 270 | uint8_t *rcrb; /* Root Complex Register Block */ |
| 271 | uint32_t rcba; /* Root Complex Base Address */ |
| 272 | uint8_t bios_cntl; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 273 | ich9_spi_regs *ich9_spi; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 274 | ich7_spi_regs *ich7_spi; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 275 | uint16_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 276 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 277 | #ifdef __SIMPLE_DEVICE__ |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 278 | pci_devfn_t dev = PCI_DEV(0, 31, 0); |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 279 | #else |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 280 | struct device *dev = pcidev_on_root(31, 0); |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 281 | #endif |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 282 | |
Kyösti Mälkki | 7ba1440 | 2019-02-07 12:44:00 +0200 | [diff] [blame] | 283 | rcba = pci_read_config32(dev, 0xf0); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 284 | /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ |
| 285 | rcrb = (uint8_t *)(rcba & 0xffffc000); |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 286 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { |
| 287 | ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 288 | cntlr->opmenu = ich7_spi->opmenu; |
| 289 | cntlr->menubytes = sizeof(ich7_spi->opmenu); |
| 290 | cntlr->optype = &ich7_spi->optype; |
| 291 | cntlr->addr = &ich7_spi->spia; |
| 292 | cntlr->data = (uint8_t *)ich7_spi->spid; |
| 293 | cntlr->databytes = sizeof(ich7_spi->spid); |
| 294 | cntlr->status = (uint8_t *)&ich7_spi->spis; |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 295 | g_ichspi_lock = readw_(&ich7_spi->spis) & HSFS_FLOCKDN; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 296 | cntlr->control = &ich7_spi->spic; |
| 297 | cntlr->bbar = &ich7_spi->bbar; |
| 298 | cntlr->preop = &ich7_spi->preop; |
| 299 | cntlr->fpr = &ich7_spi->pbr[0]; |
| 300 | cntlr->fpr_max = 3; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 301 | } else { |
| 302 | ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 303 | cntlr->ich9_spi = ich9_spi; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 304 | hsfs = readw_(&ich9_spi->hsfs); |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 305 | g_ichspi_lock = hsfs & HSFS_FLOCKDN; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 306 | cntlr->hsfs = hsfs; |
| 307 | cntlr->opmenu = ich9_spi->opmenu; |
| 308 | cntlr->menubytes = sizeof(ich9_spi->opmenu); |
| 309 | cntlr->optype = &ich9_spi->optype; |
| 310 | cntlr->addr = &ich9_spi->faddr; |
| 311 | cntlr->data = (uint8_t *)ich9_spi->fdata; |
| 312 | cntlr->databytes = sizeof(ich9_spi->fdata); |
| 313 | cntlr->status = &ich9_spi->ssfs; |
| 314 | cntlr->control = (uint16_t *)ich9_spi->ssfc; |
| 315 | cntlr->bbar = &ich9_spi->bbar; |
| 316 | cntlr->preop = &ich9_spi->preop; |
| 317 | cntlr->fpr = &ich9_spi->pr[0]; |
| 318 | cntlr->fpr_max = 5; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 319 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 320 | if (cntlr->hsfs & HSFS_FDV) { |
Patrick Georgi | c88828d | 2018-11-26 10:42:59 +0100 | [diff] [blame] | 321 | writel_(4, &ich9_spi->fdoc); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 322 | cntlr->flmap0 = readl_(&ich9_spi->fdod); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 323 | writel_(0x1000, &ich9_spi->fdoc); |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 324 | cntlr->flcomp = readl_(&ich9_spi->fdod); |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 325 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 326 | } |
| 327 | |
| 328 | ich_set_bbar(0); |
| 329 | |
| 330 | /* Disable the BIOS write protect so write commands are allowed. */ |
Kyösti Mälkki | 7ba1440 | 2019-02-07 12:44:00 +0200 | [diff] [blame] | 331 | bios_cntl = pci_read_config8(dev, 0xdc); |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 332 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 333 | bios_cntl &= ~(1 << 5); |
Kyösti Mälkki | 7ba1440 | 2019-02-07 12:44:00 +0200 | [diff] [blame] | 334 | pci_write_config8(dev, 0xdc, bios_cntl | 0x1); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 335 | } |
Aaron Durbin | 4d3de7e | 2015-09-02 17:34:04 -0500 | [diff] [blame] | 336 | |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 337 | static void spi_init_cb(void *unused) |
| 338 | { |
| 339 | spi_init(); |
| 340 | } |
| 341 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 342 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 343 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 344 | typedef struct spi_transaction { |
| 345 | const uint8_t *out; |
| 346 | uint32_t bytesout; |
| 347 | uint8_t *in; |
| 348 | uint32_t bytesin; |
| 349 | uint8_t type; |
| 350 | uint8_t opcode; |
| 351 | uint32_t offset; |
| 352 | } spi_transaction; |
| 353 | |
| 354 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 355 | { |
| 356 | trans->out += bytes; |
| 357 | trans->bytesout -= bytes; |
| 358 | } |
| 359 | |
| 360 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 361 | { |
| 362 | trans->in += bytes; |
| 363 | trans->bytesin -= bytes; |
| 364 | } |
| 365 | |
| 366 | static void spi_setup_type(spi_transaction *trans) |
| 367 | { |
| 368 | trans->type = 0xFF; |
| 369 | |
| 370 | /* Try to guess spi type from read/write sizes. */ |
| 371 | if (trans->bytesin == 0) { |
| 372 | if (trans->bytesout > 4) |
| 373 | /* |
| 374 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 375 | * a write data operation, which is accompanied by an |
| 376 | * address. |
| 377 | */ |
| 378 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 379 | else |
| 380 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 381 | return; |
| 382 | } |
| 383 | |
| 384 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 385 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 386 | return; |
| 387 | } |
| 388 | |
| 389 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 390 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 391 | } |
Duncan Laurie | 23b0053 | 2012-10-10 14:21:23 -0700 | [diff] [blame] | 392 | |
| 393 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 394 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 395 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 396 | --trans->bytesout; |
| 397 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | static int spi_setup_opcode(spi_transaction *trans) |
| 401 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 402 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 403 | uint16_t optypes; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 404 | uint8_t opmenu[cntlr->menubytes]; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 405 | |
| 406 | trans->opcode = trans->out[0]; |
| 407 | spi_use_out(trans, 1); |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 408 | if (!g_ichspi_lock) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 409 | /* The lock is off, so just use index 0. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 410 | writeb_(trans->opcode, cntlr->opmenu); |
| 411 | optypes = readw_(cntlr->optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 412 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 413 | writew_(optypes, cntlr->optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 414 | return 0; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 415 | } |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 416 | |
| 417 | /* The lock is on. See if what we need is on the menu. */ |
| 418 | uint8_t optype; |
| 419 | uint16_t opcode_index; |
| 420 | |
| 421 | /* Write Enable is handled as atomic prefix */ |
| 422 | if (trans->opcode == SPI_OPCODE_WREN) |
| 423 | return 0; |
| 424 | |
| 425 | read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); |
| 426 | for (opcode_index = 0; opcode_index < cntlr->menubytes; |
| 427 | opcode_index++) { |
| 428 | if (opmenu[opcode_index] == trans->opcode) |
| 429 | break; |
| 430 | } |
| 431 | |
| 432 | if (opcode_index == cntlr->menubytes) { |
| 433 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 434 | trans->opcode); |
| 435 | return -1; |
| 436 | } |
| 437 | |
| 438 | optypes = readw_(cntlr->optype); |
| 439 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 440 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 441 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 442 | trans->bytesout >= 3) { |
| 443 | /* We guessed wrong earlier. Fix it up. */ |
| 444 | trans->type = optype; |
| 445 | } |
| 446 | if (optype != trans->type) { |
| 447 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 448 | optype); |
| 449 | return -1; |
| 450 | } |
| 451 | return opcode_index; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 452 | } |
| 453 | |
| 454 | static int spi_setup_offset(spi_transaction *trans) |
| 455 | { |
| 456 | /* Separate the SPI address and data. */ |
| 457 | switch (trans->type) { |
| 458 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 459 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 460 | return 0; |
| 461 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 462 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 463 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 464 | ((uint32_t)trans->out[1] << 8) | |
| 465 | ((uint32_t)trans->out[2] << 0); |
| 466 | spi_use_out(trans, 3); |
| 467 | return 1; |
| 468 | default: |
| 469 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 470 | return -1; |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | /* |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 475 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 476 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 477 | * those bits back, which would cause resetting them. |
| 478 | * |
| 479 | * Return the last read status value on success or -1 on failure. |
| 480 | */ |
| 481 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 482 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 483 | ich_spi_controller *cntlr = &g_cntlr; |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 484 | int timeout = 600000; /* This will result in 6 seconds */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 485 | u16 status = 0; |
| 486 | |
| 487 | while (timeout--) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 488 | status = readw_(cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 489 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 490 | if (wait_til_set) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 491 | writew_((status & bitmask), cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 492 | return status; |
| 493 | } |
| 494 | udelay(10); |
| 495 | } |
| 496 | |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 497 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 498 | status, bitmask); |
| 499 | return -1; |
| 500 | } |
| 501 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 502 | static int spi_is_multichip(void) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 503 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 504 | ich_spi_controller *cntlr = &g_cntlr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 505 | if (!(cntlr->hsfs & HSFS_FDV)) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 506 | return 0; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 507 | return !!((cntlr->flmap0 >> 8) & 3); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 508 | } |
| 509 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 510 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 511 | size_t bytesout, void *din, size_t bytesin) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 512 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 513 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 514 | uint16_t control; |
| 515 | int16_t opcode_index; |
| 516 | int with_address; |
| 517 | int status; |
| 518 | |
| 519 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 520 | dout, bytesout, |
| 521 | din, bytesin, |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 522 | 0xff, 0xff, 0 |
| 523 | }; |
| 524 | |
| 525 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 526 | if (!bytesout || !dout) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 527 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 528 | return -1; |
| 529 | } |
| 530 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 531 | if (bytesin != 0 && !din) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 532 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 533 | return -1; |
| 534 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 535 | |
| 536 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 537 | return -1; |
| 538 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 539 | writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 540 | |
| 541 | spi_setup_type(&trans); |
| 542 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 543 | return -1; |
| 544 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 545 | return -1; |
| 546 | |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 547 | if (trans.opcode == SPI_OPCODE_WREN) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 548 | /* |
| 549 | * Treat Write Enable as Atomic Pre-Op if possible |
| 550 | * in order to prevent the Management Engine from |
| 551 | * issuing a transaction between WREN and DATA. |
| 552 | */ |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 553 | if (!g_ichspi_lock) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 554 | writew_(trans.opcode, cntlr->preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 555 | return 0; |
| 556 | } |
| 557 | |
| 558 | /* Preset control fields */ |
| 559 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 560 | |
| 561 | /* Issue atomic preop cycle if needed */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 562 | if (readw_(cntlr->preop)) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 563 | control |= SPIC_ACS; |
| 564 | |
| 565 | if (!trans.bytesout && !trans.bytesin) { |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 566 | /* SPI addresses are 24 bit only */ |
| 567 | if (with_address) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 568 | writel_(trans.offset & 0x00FFFFFF, cntlr->addr); |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 569 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 570 | /* |
| 571 | * This is a 'no data' command (like Write Enable), its |
| 572 | * bitesout size was 1, decremented to zero while executing |
| 573 | * spi_setup_opcode() above. Tell the chip to send the |
| 574 | * command. |
| 575 | */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 576 | writew_(control, cntlr->control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 577 | |
| 578 | /* wait for the result */ |
| 579 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 580 | if (status == -1) |
| 581 | return -1; |
| 582 | |
| 583 | if (status & SPIS_FCERR) { |
| 584 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 585 | return -1; |
| 586 | } |
| 587 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 588 | goto spi_xfer_exit; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 589 | } |
| 590 | |
| 591 | /* |
Paul Menzel | 9478297 | 2013-06-29 11:41:27 +0200 | [diff] [blame] | 592 | * Check if this is a write command attempting to transfer more bytes |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 593 | * than the controller can handle. Iterations for writes are not |
| 594 | * supported here because each SPI write command needs to be preceded |
| 595 | * and followed by other SPI commands, and this sequence is controlled |
| 596 | * by the SPI chip driver. |
| 597 | */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 598 | if (trans.bytesout > cntlr->databytes) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 599 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 600 | " spi_crop_chunk()?\n"); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 601 | return -1; |
| 602 | } |
| 603 | |
| 604 | /* |
| 605 | * Read or write up to databytes bytes at a time until everything has |
| 606 | * been sent. |
| 607 | */ |
| 608 | while (trans.bytesout || trans.bytesin) { |
| 609 | uint32_t data_length; |
| 610 | |
| 611 | /* SPI addresses are 24 bit only */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 612 | writel_(trans.offset & 0x00FFFFFF, cntlr->addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 613 | |
| 614 | if (trans.bytesout) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 615 | data_length = min(trans.bytesout, cntlr->databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 616 | else |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 617 | data_length = min(trans.bytesin, cntlr->databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 618 | |
| 619 | /* Program data into FDATA0 to N */ |
| 620 | if (trans.bytesout) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 621 | write_reg(trans.out, cntlr->data, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 622 | spi_use_out(&trans, data_length); |
| 623 | if (with_address) |
| 624 | trans.offset += data_length; |
| 625 | } |
| 626 | |
| 627 | /* Add proper control fields' values */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 628 | control &= ~((cntlr->databytes - 1) << 8); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 629 | control |= SPIC_DS; |
| 630 | control |= (data_length - 1) << 8; |
| 631 | |
| 632 | /* write it */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 633 | writew_(control, cntlr->control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 634 | |
| 635 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 636 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 637 | if (status == -1) |
| 638 | return -1; |
| 639 | |
| 640 | if (status & SPIS_FCERR) { |
| 641 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 642 | return -1; |
| 643 | } |
| 644 | |
| 645 | if (trans.bytesin) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 646 | read_reg(cntlr->data, trans.in, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 647 | spi_use_in(&trans, data_length); |
| 648 | if (with_address) |
| 649 | trans.offset += data_length; |
| 650 | } |
| 651 | } |
| 652 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 653 | spi_xfer_exit: |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 654 | /* Clear atomic preop now that xfer is done */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 655 | writew_(0, cntlr->preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 656 | |
| 657 | return 0; |
| 658 | } |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 659 | |
| 660 | /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ |
| 661 | static void ich_hwseq_set_addr(uint32_t addr) |
| 662 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 663 | ich_spi_controller *cntlr = &g_cntlr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 664 | uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 665 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 666 | writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 667 | } |
| 668 | |
| 669 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 670 | Resets all error flags in HSFS. |
| 671 | Returns 0 if the cycle completes successfully without errors within |
| 672 | timeout us, 1 on errors. */ |
| 673 | static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, |
| 674 | unsigned int len) |
| 675 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 676 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 677 | uint16_t hsfs; |
| 678 | uint32_t addr; |
| 679 | |
| 680 | timeout /= 8; /* scale timeout duration to counter */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 681 | while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) & |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 682 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
| 683 | --timeout) { |
| 684 | udelay(8); |
| 685 | } |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 686 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 687 | |
| 688 | if (!timeout) { |
| 689 | uint16_t hsfc; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 690 | addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; |
| 691 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 692 | printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " |
| 693 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 694 | addr, addr + len - 1, addr, len - 1, |
| 695 | hsfc, hsfs); |
| 696 | return 1; |
| 697 | } |
| 698 | |
| 699 | if (hsfs & HSFS_FCERR) { |
| 700 | uint16_t hsfc; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 701 | addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; |
| 702 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 703 | printk(BIOS_ERR, "Transaction error between offset 0x%08x and " |
| 704 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 705 | addr, addr + len - 1, addr, len - 1, |
| 706 | hsfc, hsfs); |
| 707 | return 1; |
| 708 | } |
| 709 | return 0; |
| 710 | } |
| 711 | |
| 712 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 713 | static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, |
| 714 | size_t len) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 715 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 716 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 717 | u32 start, end, erase_size; |
| 718 | int ret; |
| 719 | uint16_t hsfc; |
| 720 | uint16_t timeout = 1000 * 60; |
| 721 | |
| 722 | erase_size = flash->sector_size; |
| 723 | if (offset % erase_size || len % erase_size) { |
| 724 | printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); |
| 725 | return -1; |
| 726 | } |
| 727 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 728 | ret = spi_claim_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 729 | if (ret) { |
| 730 | printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); |
| 731 | return ret; |
| 732 | } |
| 733 | |
| 734 | start = offset; |
| 735 | end = start + len; |
| 736 | |
| 737 | while (offset < end) { |
| 738 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 739 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 740 | |
| 741 | ich_hwseq_set_addr(offset); |
| 742 | |
| 743 | offset += erase_size; |
| 744 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 745 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 746 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 747 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 748 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 749 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 750 | if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 751 | printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); |
| 752 | ret = -1; |
| 753 | goto out; |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); |
| 758 | |
| 759 | out: |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 760 | spi_release_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 761 | return ret; |
| 762 | } |
| 763 | |
| 764 | static void ich_read_data(uint8_t *data, int len) |
| 765 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 766 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 767 | int i; |
| 768 | uint32_t temp32 = 0; |
| 769 | |
| 770 | for (i = 0; i < len; i++) { |
| 771 | if ((i % 4) == 0) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 772 | temp32 = readl_(cntlr->data + i); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 773 | |
| 774 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 775 | } |
| 776 | } |
| 777 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 778 | static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, |
| 779 | void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 780 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 781 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 782 | uint16_t hsfc; |
| 783 | uint16_t timeout = 100 * 60; |
| 784 | uint8_t block_len; |
| 785 | |
| 786 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 787 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 788 | "Attempt to read %x-%x which is out of chip\n", |
| 789 | (unsigned) addr, |
| 790 | (unsigned) addr+(unsigned) len); |
| 791 | return -1; |
| 792 | } |
| 793 | |
| 794 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 795 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 796 | |
| 797 | while (len > 0) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 798 | block_len = min(len, cntlr->databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 799 | if (block_len > (~addr & 0xff)) |
| 800 | block_len = (~addr & 0xff) + 1; |
| 801 | ich_hwseq_set_addr(addr); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 802 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 803 | hsfc &= ~HSFC_FCYCLE; /* set read operation */ |
| 804 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 805 | /* set byte count */ |
| 806 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 807 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 808 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 809 | |
| 810 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 811 | return 1; |
| 812 | ich_read_data(buf, block_len); |
| 813 | addr += block_len; |
| 814 | buf += block_len; |
| 815 | len -= block_len; |
| 816 | } |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 821 | * |
| 822 | * Note that using len > flash->pgm->spi.max_data_write will trash the registers |
| 823 | * following the data registers. |
| 824 | */ |
| 825 | static void ich_fill_data(const uint8_t *data, int len) |
| 826 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 827 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 828 | uint32_t temp32 = 0; |
| 829 | int i; |
| 830 | |
| 831 | if (len <= 0) |
| 832 | return; |
| 833 | |
| 834 | for (i = 0; i < len; i++) { |
| 835 | if ((i % 4) == 0) |
| 836 | temp32 = 0; |
| 837 | |
| 838 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 839 | |
| 840 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 841 | writel_(temp32, cntlr->data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 842 | } |
| 843 | i--; |
| 844 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 845 | writel_(temp32, cntlr->data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 846 | } |
| 847 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 848 | static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, |
| 849 | const void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 850 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 851 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 852 | uint16_t hsfc; |
| 853 | uint16_t timeout = 100 * 60; |
| 854 | uint8_t block_len; |
| 855 | uint32_t start = addr; |
| 856 | |
| 857 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 858 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 859 | "Attempt to write 0x%x-0x%x which is out of chip\n", |
| 860 | (unsigned)addr, (unsigned) (addr+len)); |
| 861 | return -1; |
| 862 | } |
| 863 | |
| 864 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 865 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 866 | |
| 867 | while (len > 0) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 868 | block_len = min(len, cntlr->databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 869 | if (block_len > (~addr & 0xff)) |
| 870 | block_len = (~addr & 0xff) + 1; |
| 871 | |
| 872 | ich_hwseq_set_addr(addr); |
| 873 | |
| 874 | ich_fill_data(buf, block_len); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 875 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 876 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 877 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 878 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 879 | /* set byte count */ |
| 880 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 881 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 882 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 883 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 884 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { |
| 885 | printk(BIOS_ERR, "SF: write failure at %x\n", |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 886 | addr); |
| 887 | return -1; |
| 888 | } |
| 889 | addr += block_len; |
| 890 | buf += block_len; |
| 891 | len -= block_len; |
| 892 | } |
| 893 | printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", |
| 894 | (unsigned) (addr - start), start); |
| 895 | return 0; |
| 896 | } |
| 897 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 898 | static const struct spi_flash_ops spi_flash_ops = { |
| 899 | .read = ich_hwseq_read, |
| 900 | .write = ich_hwseq_write, |
| 901 | .erase = ich_hwseq_erase, |
| 902 | }; |
| 903 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 904 | static int spi_flash_programmer_probe(const struct spi_slave *spi, |
| 905 | struct spi_flash *flash) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 906 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 907 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 908 | |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 909 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) |
| 910 | return spi_flash_generic_probe(spi, flash); |
| 911 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 912 | /* Try generic probing first if spi_is_multichip returns 0. */ |
| 913 | if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash)) |
| 914 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 915 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 916 | memcpy(&flash->spi, spi, sizeof(*spi)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 917 | flash->name = "Opaque HW-sequencing"; |
| 918 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 919 | ich_hwseq_set_addr(0); |
| 920 | switch ((cntlr->hsfs >> 3) & 3) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 921 | case 0: |
| 922 | flash->sector_size = 256; |
| 923 | break; |
| 924 | case 1: |
| 925 | flash->sector_size = 4096; |
| 926 | break; |
| 927 | case 2: |
| 928 | flash->sector_size = 8192; |
| 929 | break; |
| 930 | case 3: |
| 931 | flash->sector_size = 65536; |
| 932 | break; |
| 933 | } |
| 934 | |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 935 | flash->size = 1 << (19 + (cntlr->flcomp & 7)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 936 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 937 | flash->ops = &spi_flash_ops; |
| 938 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 939 | if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 940 | flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 941 | printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 942 | |
Furquan Shaikh | 30221b4 | 2017-05-15 14:35:15 -0700 | [diff] [blame] | 943 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 944 | } |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 945 | |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 946 | static int xfer_vectors(const struct spi_slave *slave, |
| 947 | struct spi_op vectors[], size_t count) |
| 948 | { |
| 949 | return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); |
| 950 | } |
| 951 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 952 | #define SPI_FPR_SHIFT 12 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 953 | #define ICH7_SPI_FPR_MASK 0xfff |
| 954 | #define ICH9_SPI_FPR_MASK 0x1fff |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 955 | #define SPI_FPR_BASE_SHIFT 0 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 956 | #define ICH7_SPI_FPR_LIMIT_SHIFT 12 |
| 957 | #define ICH9_SPI_FPR_LIMIT_SHIFT 16 |
| 958 | #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 959 | #define SPI_FPR_WPE (1 << 31) /* Write Protect */ |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 960 | |
| 961 | static u32 spi_fpr(u32 base, u32 limit) |
| 962 | { |
| 963 | u32 ret; |
| 964 | u32 mask, limit_shift; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 965 | |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 966 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { |
| 967 | mask = ICH7_SPI_FPR_MASK; |
| 968 | limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; |
| 969 | } else { |
| 970 | mask = ICH9_SPI_FPR_MASK; |
| 971 | limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT; |
| 972 | } |
| 973 | ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift; |
| 974 | ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT; |
| 975 | return ret; |
| 976 | } |
| 977 | |
| 978 | /* |
| 979 | * Protect range of SPI flash defined by [start, start+size-1] using Flash |
| 980 | * Protected Range (FPR) register if available. |
| 981 | * Returns 0 on success, -1 on failure of programming fpr registers. |
| 982 | */ |
| 983 | static int spi_flash_protect(const struct spi_flash *flash, |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 984 | const struct region *region, |
| 985 | const enum ctrlr_prot_type type) |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 986 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 987 | ich_spi_controller *cntlr = &g_cntlr; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 988 | u32 start = region_offset(region); |
| 989 | u32 end = start + region_sz(region) - 1; |
| 990 | u32 reg; |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 991 | u32 protect_mask = 0; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 992 | int fpr; |
| 993 | uint32_t *fpr_base; |
| 994 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 995 | fpr_base = cntlr->fpr; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 996 | |
| 997 | /* Find first empty FPR */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 998 | for (fpr = 0; fpr < cntlr->fpr_max; fpr++) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 999 | reg = read32(&fpr_base[fpr]); |
| 1000 | if (reg == 0) |
| 1001 | break; |
| 1002 | } |
| 1003 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1004 | if (fpr == cntlr->fpr_max) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1005 | printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); |
| 1006 | return -1; |
| 1007 | } |
| 1008 | |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1009 | switch (type) { |
| 1010 | case WRITE_PROTECT: |
| 1011 | protect_mask |= SPI_FPR_WPE; |
| 1012 | break; |
| 1013 | case READ_PROTECT: |
| 1014 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) |
| 1015 | return -1; |
| 1016 | protect_mask |= ICH9_SPI_FPR_RPE; |
| 1017 | break; |
| 1018 | case READ_WRITE_PROTECT: |
| 1019 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) |
| 1020 | return -1; |
| 1021 | protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); |
| 1022 | break; |
| 1023 | default: |
| 1024 | printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); |
| 1025 | return -1; |
| 1026 | } |
| 1027 | |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1028 | /* Set protected range base and limit */ |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1029 | reg = spi_fpr(start, end) | protect_mask; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1030 | |
| 1031 | /* Set the FPR register and verify it is protected */ |
| 1032 | write32(&fpr_base[fpr], reg); |
| 1033 | reg = read32(&fpr_base[fpr]); |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1034 | if (!(reg & protect_mask)) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1035 | printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); |
| 1036 | return -1; |
| 1037 | } |
| 1038 | |
| 1039 | printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", |
| 1040 | __func__, fpr, start, end); |
| 1041 | return 0; |
| 1042 | } |
| 1043 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1044 | static const struct spi_ctrlr spi_ctrlr = { |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 1045 | .xfer_vector = xfer_vectors, |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1046 | .max_xfer_size = member_size(ich9_spi_regs, fdata), |
| 1047 | .flash_probe = spi_flash_programmer_probe, |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1048 | .flash_protect = spi_flash_protect, |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1049 | }; |
| 1050 | |
Furquan Shaikh | 2cd03f1 | 2017-05-18 14:58:32 -0700 | [diff] [blame] | 1051 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 1052 | { |
| 1053 | .ctrlr = &spi_ctrlr, |
| 1054 | .bus_start = 0, |
| 1055 | .bus_end = 0, |
| 1056 | }, |
| 1057 | }; |
| 1058 | |
| 1059 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |