Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 5 | #include <soc/iosf.h> |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 6 | #include <soc/iomap.h> |
| 7 | #include <soc/gpio.h> |
| 8 | #include <soc/lpc.h> |
| 9 | #include <soc/spi.h> |
Angel Pons | b5320b2 | 2020-07-07 18:27:30 +0200 | [diff] [blame] | 10 | #include <soc/pm.h> |
Aaron Durbin | ba170b47 | 2013-09-23 14:15:42 -0500 | [diff] [blame] | 11 | |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 12 | static void setup_mmconfig(void) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 13 | { |
| 14 | uint32_t reg; |
| 15 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 16 | /* |
| 17 | * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the |
| 18 | * config access needs to be used initially to properly configure as the IOSF access |
| 19 | * registers live in PCI config space. |
| 20 | */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 21 | reg = 0; |
| 22 | /* Clear the extended register. */ |
| 23 | pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); |
| 24 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; |
| 25 | pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); |
| 26 | reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | |
| 27 | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; |
| 28 | pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); |
| 29 | } |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 30 | |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 31 | static void program_base_addresses(void) |
| 32 | { |
| 33 | uint32_t reg; |
| 34 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 35 | |
| 36 | /* Memory Mapped IO registers. */ |
| 37 | reg = PMC_BASE_ADDRESS | 2; |
| 38 | pci_write_config32(lpc_dev, PBASE, reg); |
| 39 | reg = IO_BASE_ADDRESS | 2; |
| 40 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 41 | reg = ILB_BASE_ADDRESS | 2; |
| 42 | pci_write_config32(lpc_dev, IBASE, reg); |
| 43 | reg = SPI_BASE_ADDRESS | 2; |
| 44 | pci_write_config32(lpc_dev, SBASE, reg); |
| 45 | reg = MPHY_BASE_ADDRESS | 2; |
| 46 | pci_write_config32(lpc_dev, MPBASE, reg); |
| 47 | reg = PUNIT_BASE_ADDRESS | 2; |
| 48 | pci_write_config32(lpc_dev, PUBASE, reg); |
| 49 | reg = RCBA_BASE_ADDRESS | 1; |
| 50 | pci_write_config32(lpc_dev, RCBA, reg); |
| 51 | |
| 52 | /* IO Port Registers. */ |
| 53 | reg = ACPI_BASE_ADDRESS | 2; |
| 54 | pci_write_config32(lpc_dev, ABASE, reg); |
| 55 | reg = GPIO_BASE_ADDRESS | 2; |
| 56 | pci_write_config32(lpc_dev, GBASE, reg); |
| 57 | } |
| 58 | |
| 59 | static void spi_init(void) |
| 60 | { |
Angel Pons | e80d17f | 2020-07-07 17:25:38 +0200 | [diff] [blame^] | 61 | void *scs = (void *)(SPI_BASE_ADDRESS + SCS); |
| 62 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 63 | uint32_t reg; |
| 64 | |
| 65 | /* Disable generating SMI when setting WPD bit. */ |
| 66 | write32(scs, read32(scs) & ~SMIWPEN); |
| 67 | /* |
| 68 | * Enable caching and prefetching in the SPI controller. Disable |
| 69 | * the SMM-only BIOS write and set WPD bit. |
| 70 | */ |
| 71 | reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; |
| 72 | reg &= ~EISS; |
| 73 | write32(bcr, reg); |
| 74 | } |
| 75 | |
| 76 | static void tco_disable(void) |
| 77 | { |
| 78 | uint32_t reg; |
| 79 | |
| 80 | reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); |
| 81 | reg |= TCO_TMR_HALT; |
| 82 | outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); |
| 83 | } |
| 84 | |
| 85 | static void byt_config_com1_and_enable(void) |
| 86 | { |
| 87 | uint32_t reg; |
| 88 | |
| 89 | /* Enable the UART hardware for COM1. */ |
| 90 | reg = 1; |
| 91 | pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); |
| 92 | |
| 93 | /* Set up the pads to select the UART function */ |
| 94 | score_select_func(UART_RXD_PAD, 1); |
| 95 | score_select_func(UART_TXD_PAD, 1); |
| 96 | } |
| 97 | |
| 98 | /* The distinction between nb/sb/cpu is not applicable here so |
| 99 | just pick the one that is called first. */ |
| 100 | void bootblock_early_northbridge_init(void) |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 101 | { |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 102 | /* Allow memory-mapped PCI config access */ |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 103 | setup_mmconfig(); |
| 104 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 105 | /* Early chipset initialization */ |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 106 | program_base_addresses(); |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 107 | tco_disable(); |
| 108 | |
| 109 | if (CONFIG(ENABLE_BUILTIN_COM1)) |
| 110 | byt_config_com1_and_enable(); |
| 111 | |
| 112 | spi_init(); |
Aaron Durbin | c0270aa | 2013-10-04 11:15:48 -0500 | [diff] [blame] | 113 | } |