src/cpu/amd/agesa/Kconfig

#
# This file is part of the coreboot project.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#

config CPU_AMD_AGESA
	bool
	default y if CPU_AMD_AGESA_FAMILY14
	default y if CPU_AMD_AGESA_FAMILY15_TN
	default y if CPU_AMD_AGESA_FAMILY16_KB
	default n
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32
	select DRIVERS_AMD_PI
	select TSC_SYNC_LFENCE
	select UDELAY_LAPIC
	select LAPIC_MONOTONIC_TIMER
	select SPI_FLASH if HAVE_ACPI_RESUME
	select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
	select SMM_ASEG
	select NO_FIXED_XIP_ROM_SIZE

if CPU_AMD_AGESA

config UDELAY_LAPIC_FIXED_FSB
	int
	default 200

# TODO: Sync these with definitions in AGESA vendorcode.
# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.

config DCACHE_RAM_BASE
	hex
	default 0x30000

config DCACHE_RAM_SIZE
	hex
	default 0x10000

config ENABLE_MRC_CACHE
	bool "Use cached memory configuration"
	default n
	select SPI_FLASH
	help
	  Try to restore memory training results
	  from non-volatile memory.

config S3_DATA_POS
	hex
	default 0xFFFF0000

config S3_DATA_SIZE
	int
	default 32768

endif # CPU_AMD_AGESA

source "src/cpu/amd/agesa/family14/Kconfig"
source "src/cpu/amd/agesa/family15tn/Kconfig"
source "src/cpu/amd/agesa/family16kb/Kconfig"