Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 4 | # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 15 | |
Kyösti Mälkki | d11ca1d | 2012-03-16 15:40:56 +0200 | [diff] [blame] | 16 | config CPU_AMD_AGESA |
Paul Menzel | ea23a6b | 2013-05-02 10:34:49 +0200 | [diff] [blame] | 17 | bool |
Paul Menzel | ea23a6b | 2013-05-02 10:34:49 +0200 | [diff] [blame] | 18 | default y if CPU_AMD_AGESA_FAMILY12 |
| 19 | default y if CPU_AMD_AGESA_FAMILY14 |
| 20 | default y if CPU_AMD_AGESA_FAMILY15 |
| 21 | default y if CPU_AMD_AGESA_FAMILY15_TN |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 22 | default y if CPU_AMD_AGESA_FAMILY16_KB |
Paul Menzel | ea23a6b | 2013-05-02 10:34:49 +0200 | [diff] [blame] | 23 | default n |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 24 | select ARCH_BOOTBLOCK_X86_32 |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 25 | select ARCH_VERSTAGE_X86_32 |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 26 | select ARCH_ROMSTAGE_X86_32 |
| 27 | select ARCH_RAMSTAGE_X86_32 |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame^] | 28 | select DRIVERS_AMD_PI |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 29 | select TSC_SYNC_LFENCE |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 30 | select UDELAY_LAPIC |
Paul Menzel | 60c54cc | 2013-05-01 16:36:56 +0200 | [diff] [blame] | 31 | select LAPIC_MONOTONIC_TIMER |
Kyösti Mälkki | bb6c216 | 2014-04-29 07:15:26 +0300 | [diff] [blame] | 32 | select SPI_FLASH if HAVE_ACPI_RESUME |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 33 | select POSTCAR_STAGE if !AGESA_LEGACY_WRAPPER |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 34 | |
Kyösti Mälkki | d11ca1d | 2012-03-16 15:40:56 +0200 | [diff] [blame] | 35 | if CPU_AMD_AGESA |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 36 | |
Kyösti Mälkki | 967d94d | 2016-11-22 11:52:14 +0200 | [diff] [blame] | 37 | config AGESA_LEGACY |
| 38 | def_bool n |
| 39 | |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 40 | config AGESA_LEGACY_WRAPPER |
| 41 | bool |
| 42 | default AGESA_LEGACY |
| 43 | |
Kyösti Mälkki | 967d94d | 2016-11-22 11:52:14 +0200 | [diff] [blame] | 44 | config AGESA_NO_LEGACY |
| 45 | bool |
| 46 | default !AGESA_LEGACY |
| 47 | |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 48 | config XIP_ROM_SIZE |
| 49 | hex |
| 50 | default 0x100000 |
| 51 | help |
| 52 | Overwride the default write through caching size as 1M Bytes. |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 53 | On some AMD platforms, one socket supports 2 or more kinds of |
| 54 | processor family, compiling several CPU families agesa code |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 55 | will increase the romstage size. |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 56 | In order to execute romstage in place on the flash ROM, |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 57 | more space is required to be set as write through caching. |
| 58 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 59 | config UDELAY_LAPIC_FIXED_FSB |
| 60 | int |
| 61 | default 200 |
| 62 | |
Kyösti Mälkki | c984f4f | 2013-07-29 10:16:14 +0300 | [diff] [blame] | 63 | # TODO: Sync these with definitions in AGESA vendorcode. |
| 64 | # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| 65 | # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| 66 | |
| 67 | config DCACHE_RAM_BASE |
| 68 | hex |
| 69 | default 0x30000 |
| 70 | |
| 71 | config DCACHE_RAM_SIZE |
| 72 | hex |
| 73 | default 0x10000 |
Kyösti Mälkki | 4f7cb87 | 2014-06-19 03:48:42 +0300 | [diff] [blame] | 74 | |
| 75 | config S3_DATA_POS |
| 76 | hex |
| 77 | default 0xFFFF0000 |
| 78 | |
| 79 | config S3_DATA_SIZE |
| 80 | int |
| 81 | default 32768 |
| 82 | |
Patrick Georgi | 5d41c1a | 2014-04-12 13:04:14 +0200 | [diff] [blame] | 83 | endif # CPU_AMD_AGESA |
Kyösti Mälkki | c984f4f | 2013-07-29 10:16:14 +0300 | [diff] [blame] | 84 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 85 | source src/cpu/amd/agesa/family12/Kconfig |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 86 | source src/cpu/amd/agesa/family14/Kconfig |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 87 | source src/cpu/amd/agesa/family15/Kconfig |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 88 | source src/cpu/amd/agesa/family15tn/Kconfig |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 89 | source src/cpu/amd/agesa/family16kb/Kconfig |