Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 4 | # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU General Public License |
| 16 | # along with this program; if not, write to the Free Software |
| 17 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | # |
| 19 | |
Kyösti Mälkki | d11ca1d | 2012-03-16 15:40:56 +0200 | [diff] [blame] | 20 | config CPU_AMD_AGESA |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 21 | bool |
Kyösti Mälkki | d11ca1d | 2012-03-16 15:40:56 +0200 | [diff] [blame] | 22 | default y if CPU_AMD_AGESA_FAMILY10 |
| 23 | default y if CPU_AMD_AGESA_FAMILY12 |
| 24 | default y if CPU_AMD_AGESA_FAMILY14 |
Kyösti Mälkki | f5bb477 | 2012-03-16 15:15:20 +0200 | [diff] [blame] | 25 | default y if CPU_AMD_AGESA_FAMILY15 |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 26 | default y if CPU_AMD_AGESA_FAMILY15_TN |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 27 | default n |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 28 | select TSC_SYNC_LFENCE |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame^] | 29 | select UDELAY_LAPIC |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 30 | |
Kyösti Mälkki | d11ca1d | 2012-03-16 15:40:56 +0200 | [diff] [blame] | 31 | if CPU_AMD_AGESA |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 32 | |
Stefan Reinauer | 40f36e0 | 2012-11-15 16:03:27 -0800 | [diff] [blame] | 33 | config UDELAY_IO |
| 34 | bool |
| 35 | default n |
| 36 | |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 37 | config XIP_ROM_SIZE |
| 38 | hex |
| 39 | default 0x100000 |
| 40 | help |
| 41 | Overwride the default write through caching size as 1M Bytes. |
| 42 | On some AMD paltform, one socket support 2 or more kinds of |
| 43 | processor family, compiling several cpu families agesa code |
| 44 | will increase the romstage size. |
| 45 | In order to execute romstage in place on the flash rom, |
| 46 | more space is required to be set as write through caching. |
| 47 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame^] | 48 | config UDELAY_LAPIC_FIXED_FSB |
| 49 | int |
| 50 | default 200 |
| 51 | |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 52 | source src/cpu/amd/agesa/family10/Kconfig |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 53 | source src/cpu/amd/agesa/family12/Kconfig |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 54 | source src/cpu/amd/agesa/family14/Kconfig |
Kerry Sheh | d3e990c | 2012-02-07 20:31:35 +0800 | [diff] [blame] | 55 | source src/cpu/amd/agesa/family15/Kconfig |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 56 | source src/cpu/amd/agesa/family15tn/Kconfig |
Kyösti Mälkki | f5bb477 | 2012-03-16 15:15:20 +0200 | [diff] [blame] | 57 | |
Kyösti Mälkki | d11ca1d | 2012-03-16 15:40:56 +0200 | [diff] [blame] | 58 | endif # CPU_AMD_AGESA |