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review.coreboot.org / coreboot / ba38f37d185cd2c795e7f0247e815a1c2dd3df98 / . / src / soc / intel / common / block / pcie / pcie.c
blob: 153e7f79271551a353bb981945604448559cb6be [file] [log] [blame]
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <console/console.h>
16#include <device/pci.h>
17#include <device/pciexp.h>
18#include <device/pci_def.h>
19#include <device/pci_ids.h>
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]20#include <device/pci_ops.h>
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]21
22#define CACHE_LINE_SIZE 0x10
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]23
24static void pch_pcie_init(struct device *dev)
25{
26 u16 reg16;
27
28 printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
29
30 /* Enable SERR */
31 pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
32
33 /* Enable Bus Master */
34 pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
35
36 /* Set Cache Line Size to 0x10 */
37 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
38
39 /* disable parity error response, enable ISA */
Kyösti Mälkkidf128a52019-09-21 18:35:37 +0300[diff] [blame]40 pci_update_config16(dev, PCI_BRIDGE_CONTROL,
41 ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]42
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]43 if (CONFIG(PCIE_DEBUG_INFO)) {
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]44 printk(BIOS_SPEW, " MBL = 0x%08x\n",
45 pci_read_config32(dev, PCI_MEMORY_BASE));
46 printk(BIOS_SPEW, " PMBL = 0x%08x\n",
47 pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
48 printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
49 pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
50 printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
51 pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
52 }
53
54 /* Clear errors in status registers */
55 reg16 = pci_read_config16(dev, PCI_STATUS);
56 pci_write_config16(dev, PCI_STATUS, reg16);
57 reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
58 pci_write_config16(dev, PCI_SEC_STATUS, reg16);
59}
60
Elyes HAOUAS4a131262018-09-16 17:35:48 +0200[diff] [blame]61static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]62{
63 /* Set max snoop and non-snoop latency for the SOC */
64 pci_write_config32(dev, offset,
Subrata Baniked6996f2019-03-25 21:49:39 +0530[diff] [blame]65 PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
66 PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]67}
68
69static struct pci_operations pcie_ops = {
70 .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
Subrata Banik15ccbf02019-03-20 15:09:44 +0530[diff] [blame]71 .set_subsystem = pci_dev_set_subsystem,
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]72};
73
74static struct device_operations device_ops = {
75 .read_resources = pci_bus_read_resources,
76 .set_resources = pci_dev_set_resources,
77 .enable_resources = pci_bus_enable_resources,
78 .init = pch_pcie_init,
79 .scan_bus = pciexp_scan_bridge,
80 .ops_pci = &pcie_ops,
81};
82
83static const unsigned short pcie_device_ids[] = {
84 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1,
85 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2,
86 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3,
87 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4,
88 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5,
89 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6,
90 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7,
91 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8,
92 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9,
93 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10,
94 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11,
95 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12,
96 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1,
97 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2,
98 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3,
99 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4,
100 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5,
101 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6,
102 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7,
103 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8,
104 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9,
105 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10,
106 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11,
107 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12,
108 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13,
109 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14,
110 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15,
111 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16,
112 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17,
113 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18,
114 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19,
115 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20,
Maxim Polyakov571d07d2019-08-22 13:11:32 +0300[diff] [blame]116 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1,
117 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2,
118 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3,
119 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4,
120 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5,
121 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6,
122 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7,
123 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8,
124 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9,
125 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10,
126 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11,
127 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12,
128 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13,
129 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14,
130 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15,
131 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16,
132 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17,
133 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18,
134 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19,
135 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20,
136 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1_SUPER,
137 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2_SUPER,
138 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3_SUPER,
139 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4_SUPER,
140 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5_SUPER,
141 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6_SUPER,
142 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7_SUPER,
143 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8_SUPER,
144 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9_SUPER,
145 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10_SUPER,
146 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11_SUPER,
147 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12_SUPER,
148 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13_SUPER,
149 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14_SUPER,
150 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15_SUPER,
151 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16_SUPER,
152 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17_SUPER,
153 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18_SUPER,
154 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER,
155 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER,
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]156 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1,
157 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2,
158 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3,
159 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4,
160 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5,
161 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6,
162 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7,
163 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8,
164 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9,
165 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10,
166 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11,
167 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12,
168 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13,
169 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14,
170 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15,
171 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16,
172 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17,
173 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18,
174 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19,
175 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20,
176 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21,
177 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22,
178 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23,
179 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24,
Lijian Zhaobbedef92017-07-29 16:38:38 -0700[diff] [blame]180 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1,
181 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2,
182 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3,
183 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4,
184 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5,
185 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6,
186 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7,
187 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8,
188 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9,
189 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10,
190 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11,
191 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12,
192 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13,
193 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
194 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
195 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +0800[diff] [blame]196 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1,
197 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2,
198 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3,
199 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4,
200 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5,
201 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6,
202 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7,
203 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8,
204 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9,
205 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10,
206 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11,
207 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12,
208 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13,
209 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14,
210 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15,
211 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16,
212 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17,
213 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18,
214 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19,
215 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20,
216 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21,
217 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22,
218 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23,
219 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24,
Aamir Bohra9eac0392018-06-30 12:07:04 +0530[diff] [blame]220 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1,
221 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2,
222 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3,
223 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4,
224 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5,
225 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6,
226 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7,
227 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8,
228 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9,
229 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10,
230 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11,
231 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12,
232 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13,
233 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14,
234 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15,
235 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16,
Ronak Kanabarda7ffb482019-02-05 01:51:13 +0530[diff] [blame]236 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1,
237 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2,
238 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3,
239 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4,
240 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5,
241 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6,
242 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7,
243 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8,
244 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9,
245 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10,
246 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11,
247 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12,
248 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13,
249 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14,
250 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15,
251 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16,
Gaggery Tsai12a651c2019-12-05 11:23:20 -0800[diff] [blame]252 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1,
253 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2,
254 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3,
255 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4,
256 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5,
257 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6,
258 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7,
259 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8,
260 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9,
261 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10,
262 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11,
263 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12,
264 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13,
265 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14,
266 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15,
267 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16,
268 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17,
269 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18,
270 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19,
271 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20,
272 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21,
273 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22,
274 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23,
275 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24,
Ravi Sarawadi6b5bf402019-10-21 22:25:04 -0700[diff] [blame]276 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1,
277 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2,
278 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3,
279 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4,
280 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5,
281 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6,
282 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7,
283 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8,
284 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9,
285 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10,
286 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11,
287 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12,
288 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13,
289 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14,
290 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15,
291 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16,
Tan, Lean Sheng26136092020-01-20 19:13:56 -0800[diff] [blame]292 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1,
293 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2,
294 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3,
295 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4,
296 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5,
297 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6,
298 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7,
Meera Ravindranath3f4af0d2020-02-12 16:01:22 +0530[diff] [blame]299 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1,
300 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2,
301 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3,
302 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4,
303 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5,
304 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6,
305 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7,
306 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8,
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]307 0
308};
309
310static const struct pci_driver pch_pcie __pci_driver = {
311 .ops = &device_ops,
312 .vendor = PCI_VENDOR_ID_INTEL,
313 .devices = pcie_device_ids,
314};