Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_TIGERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Tigerlake support |
| 5 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 6 | if SOC_INTEL_TIGERLAKE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 11 | select ARCH_ALL_STAGES_X86_32 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
Alex Levin | f3668fc | 2020-06-11 20:09:45 -0700 | [diff] [blame] | 14 | select CPU_INTEL_COMMON |
Tim Wawrzynczak | 0cded1f | 2020-09-01 16:11:48 -0600 | [diff] [blame] | 15 | select CPU_INTEL_COMMON_HYPERTHREADING |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 16 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Karthikeyan Ramasubramanian | 6abee84 | 2020-06-16 23:29:28 -0600 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 18 | select FSP_M_XIP |
| 19 | select GENERIC_GPIO_LIB |
| 20 | select HAVE_FSP_GOP |
| 21 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 22 | select HAVE_SMI_HANDLER |
| 23 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 7fbcdb3 | 2020-09-16 11:39:01 -0700 | [diff] [blame] | 24 | select INTEL_CAR_NEM |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 25 | select INTEL_GMA_ACPI |
| 26 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 27 | select IOAPIC |
| 28 | select MRC_SETTINGS_PROTECT |
| 29 | select PARALLEL_MP |
| 30 | select PARALLEL_MP_AP_WORK |
| 31 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 32 | select PLATFORM_USES_FSP2_2 |
Jonathan Zhang | 01e3855 | 2020-06-17 16:03:18 -0700 | [diff] [blame] | 33 | select FSP_PEIM_TO_PEIM_INTERFACE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 34 | select REG_SCRIPT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 35 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 36 | select SOC_INTEL_COMMON |
| 37 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 38 | select SOC_INTEL_COMMON_BLOCK |
| 39 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 40 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 41 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 42 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Tim Wawrzynczak | c5316ec | 2020-05-29 15:20:56 -0600 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_DTT |
Nick Vaccaro | ef8258a | 2019-12-09 22:11:33 -0800 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 46 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 47 | select SOC_INTEL_COMMON_BLOCK_SA |
| 48 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 49 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
| 50 | select SOC_INTEL_COMMON_PCH_BASE |
| 51 | select SOC_INTEL_COMMON_RESET |
Arthur Heymans | c6872f5 | 2019-11-11 12:29:56 +0100 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_CAR |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 54 | select SSE2 |
| 55 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 56 | select TSC_MONOTONIC_TIMER |
| 57 | select UDELAY_TSC |
| 58 | select UDK_2017_BINDING |
| 59 | select DISPLAY_FSP_VERSION_INFO |
| 60 | select HECI_DISABLE_USING_SMM |
| 61 | |
| 62 | config DCACHE_RAM_BASE |
| 63 | default 0xfef00000 |
| 64 | |
| 65 | config DCACHE_RAM_SIZE |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 66 | default 0x80000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 67 | help |
| 68 | The size of the cache-as-ram region required during bootblock |
| 69 | and/or romstage. |
| 70 | |
| 71 | config DCACHE_BSP_STACK_SIZE |
| 72 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 73 | default 0x40400 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 74 | help |
| 75 | The amount of anticipated stack usage in CAR by bootblock and |
| 76 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 77 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 78 | (~1KiB). |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 79 | |
| 80 | config FSP_TEMP_RAM_SIZE |
| 81 | hex |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 82 | default 0x20000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 83 | help |
| 84 | The amount of anticipated heap usage in CAR by FSP. |
| 85 | Refer to Platform FSP integration guide document to know |
| 86 | the exact FSP requirement for Heap setup. |
| 87 | |
| 88 | config IFD_CHIPSET |
| 89 | string |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 90 | default "tgl" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 91 | |
| 92 | config IED_REGION_SIZE |
| 93 | hex |
| 94 | default 0x400000 |
| 95 | |
| 96 | config HEAP_SIZE |
| 97 | hex |
Duncan Laurie | aab226c | 2020-06-08 17:36:21 -0700 | [diff] [blame] | 98 | default 0x10000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 99 | |
| 100 | config MAX_ROOT_PORTS |
| 101 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 102 | default 12 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 103 | |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 104 | config MAX_PCIE_CLOCKS |
| 105 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 106 | default 7 |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 107 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 108 | config SMM_TSEG_SIZE |
| 109 | hex |
| 110 | default 0x800000 |
| 111 | |
| 112 | config SMM_RESERVED_SIZE |
| 113 | hex |
| 114 | default 0x200000 |
| 115 | |
| 116 | config PCR_BASE_ADDRESS |
| 117 | hex |
| 118 | default 0xfd000000 |
| 119 | help |
| 120 | This option allows you to select MMIO Base Address of sideband bus. |
| 121 | |
| 122 | config MMCONF_BASE_ADDRESS |
| 123 | hex |
| 124 | default 0xc0000000 |
| 125 | |
| 126 | config CPU_BCLK_MHZ |
| 127 | int |
| 128 | default 100 |
| 129 | |
| 130 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 131 | int |
| 132 | default 120 |
| 133 | |
| 134 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 135 | int |
| 136 | default 133 |
| 137 | |
| 138 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 139 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 140 | default 4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 141 | |
| 142 | config SOC_INTEL_I2C_DEV_MAX |
| 143 | int |
| 144 | default 6 |
| 145 | |
| 146 | config SOC_INTEL_UART_DEV_MAX |
| 147 | int |
| 148 | default 3 |
| 149 | |
| 150 | config CONSOLE_UART_BASE_ADDRESS |
| 151 | hex |
| 152 | default 0xfe032000 |
| 153 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 154 | |
| 155 | # Clock divider parameters for 115200 baud rate |
Ravi Sarawadi | 3838701 | 2019-12-19 15:04:58 -0800 | [diff] [blame] | 156 | # Baudrate = (UART source clcok * M) /(N *16) |
| 157 | # TGL UART source clock: 120MHz |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 158 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 159 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 160 | default 0x25a |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 161 | |
| 162 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 163 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 164 | default 0x7fff |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 165 | |
| 166 | config CHROMEOS |
| 167 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 168 | |
Jes Klinke | e046b71 | 2020-08-19 14:01:30 -0700 | [diff] [blame] | 169 | # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection |
| 170 | # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. |
| 171 | config TPM_CR50 |
| 172 | select CR50_USE_LONG_INTERRUPT_PULSES |
| 173 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 174 | config VBOOT |
| 175 | select VBOOT_SEPARATE_VERSTAGE |
| 176 | select VBOOT_MUST_REQUEST_DISPLAY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 177 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 178 | select VBOOT_VBNV_CMOS |
| 179 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 180 | |
| 181 | config C_ENV_BOOTBLOCK_SIZE |
| 182 | hex |
| 183 | default 0xC000 |
| 184 | |
| 185 | config CBFS_SIZE |
| 186 | hex |
| 187 | default 0x200000 |
| 188 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 189 | config FSP_HEADER_PATH |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 190 | default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 191 | |
| 192 | config FSP_FD_PATH |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 193 | default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 194 | |
Subrata Banik | 56626cf | 2020-02-27 19:39:22 +0530 | [diff] [blame] | 195 | config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT |
| 196 | int "Debug Consent for TGL" |
| 197 | # USB DBC is more common for developers so make this default to 3 if |
| 198 | # SOC_INTEL_DEBUG_CONSENT=y |
| 199 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 200 | default 0 |
| 201 | help |
| 202 | This is to control debug interface on SOC. |
| 203 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 204 | PlatformDebugConsent in FspmUpd.h has the details. |
| 205 | |
| 206 | Desired platform debug type are |
| 207 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 208 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 209 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | ebf1daa | 2020-05-19 12:32:41 +0530 | [diff] [blame] | 210 | |
| 211 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 212 | hex |
Anil Kumar | 033038f | 2020-09-08 16:18:45 -0700 | [diff] [blame] | 213 | default 0x2000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 214 | endif |