Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * This is a ramstage driver for the Intel Management Engine found in the |
| 5 | * 6-series chipset. It handles the required boot-time messages over the |
| 6 | * MMIO-based Management Engine Interface to tell the ME that the BIOS is |
| 7 | * finished with POST. Additional messages are defined for debug but are |
| 8 | * not used unless the console loglevel is high enough. |
| 9 | */ |
| 10 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 11 | #include <acpi/acpi.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 12 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | #include <console/console.h> |
Stefan Reinauer | 24d1d4b | 2013-03-21 11:51:41 -0700 | [diff] [blame] | 15 | #include <device/device.h> |
| 16 | #include <device/pci.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 17 | #include <device/pci_ids.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <string.h> |
| 20 | #include <delay.h> |
| 21 | #include <elog.h> |
Elyes HAOUAS | 400f9ca | 2019-06-23 07:01:22 +0200 | [diff] [blame] | 22 | #include <stdlib.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 24 | #include "chip.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | #include "me.h" |
| 26 | #include "pch.h" |
| 27 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | #include <vendorcode/google/chromeos/chromeos.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | /* Path that the BIOS should take based on ME state */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 31 | static const char *const me_bios_path_values[] = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | [ME_NORMAL_BIOS_PATH] = "Normal", |
| 33 | [ME_S3WAKE_BIOS_PATH] = "S3 Wake", |
| 34 | [ME_ERROR_BIOS_PATH] = "Error", |
| 35 | [ME_RECOVERY_BIOS_PATH] = "Recovery", |
| 36 | [ME_DISABLE_BIOS_PATH] = "Disable", |
| 37 | [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", |
| 38 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 39 | |
| 40 | /* MMIO base address for MEI interface */ |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 41 | static u8 *mei_base_address; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | static void mei_dump(void *ptr, int dword, int offset, const char *type) |
| 44 | { |
| 45 | struct mei_csr *csr; |
| 46 | |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 47 | if (!CONFIG(DEBUG_INTEL_ME)) |
| 48 | return; |
| 49 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 50 | printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); |
| 51 | |
| 52 | switch (offset) { |
| 53 | case MEI_H_CSR: |
| 54 | case MEI_ME_CSR_HA: |
| 55 | csr = ptr; |
| 56 | if (!csr) { |
| 57 | printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); |
| 58 | break; |
| 59 | } |
| 60 | printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " |
| 61 | "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, |
| 62 | csr->buffer_read_ptr, csr->buffer_write_ptr, |
| 63 | csr->ready, csr->reset, csr->interrupt_generate, |
| 64 | csr->interrupt_status, csr->interrupt_enable); |
| 65 | break; |
| 66 | case MEI_ME_CB_RW: |
| 67 | case MEI_H_CB_WW: |
| 68 | printk(BIOS_SPEW, "CB: 0x%08x\n", dword); |
| 69 | break; |
| 70 | default: |
| 71 | printk(BIOS_SPEW, "0x%08x\n", offset); |
| 72 | break; |
| 73 | } |
| 74 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * ME/MEI access helpers using memcpy to avoid aliasing. |
| 78 | */ |
| 79 | |
| 80 | static inline void mei_read_dword_ptr(void *ptr, int offset) |
| 81 | { |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 82 | u32 dword = read32(mei_base_address + offset); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | memcpy(ptr, &dword, sizeof(dword)); |
| 84 | mei_dump(ptr, dword, offset, "READ"); |
| 85 | } |
| 86 | |
| 87 | static inline void mei_write_dword_ptr(void *ptr, int offset) |
| 88 | { |
| 89 | u32 dword = 0; |
| 90 | memcpy(&dword, ptr, sizeof(dword)); |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 91 | write32(mei_base_address + offset, dword); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 92 | mei_dump(ptr, dword, offset, "WRITE"); |
| 93 | } |
| 94 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 95 | static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 96 | { |
| 97 | u32 dword = pci_read_config32(dev, offset); |
| 98 | memcpy(ptr, &dword, sizeof(dword)); |
| 99 | mei_dump(ptr, dword, offset, "PCI READ"); |
| 100 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | |
| 102 | static inline void read_host_csr(struct mei_csr *csr) |
| 103 | { |
| 104 | mei_read_dword_ptr(csr, MEI_H_CSR); |
| 105 | } |
| 106 | |
| 107 | static inline void write_host_csr(struct mei_csr *csr) |
| 108 | { |
| 109 | mei_write_dword_ptr(csr, MEI_H_CSR); |
| 110 | } |
| 111 | |
| 112 | static inline void read_me_csr(struct mei_csr *csr) |
| 113 | { |
| 114 | mei_read_dword_ptr(csr, MEI_ME_CSR_HA); |
| 115 | } |
| 116 | |
| 117 | static inline void write_cb(u32 dword) |
| 118 | { |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 119 | write32(mei_base_address + MEI_H_CB_WW, dword); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 120 | mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); |
| 121 | } |
| 122 | |
| 123 | static inline u32 read_cb(void) |
| 124 | { |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 125 | u32 dword = read32(mei_base_address + MEI_ME_CB_RW); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); |
| 127 | return dword; |
| 128 | } |
| 129 | |
| 130 | /* Wait for ME ready bit to be asserted */ |
| 131 | static int mei_wait_for_me_ready(void) |
| 132 | { |
| 133 | struct mei_csr me; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 134 | unsigned int try = ME_RETRY; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | |
| 136 | while (try--) { |
| 137 | read_me_csr(&me); |
| 138 | if (me.ready) |
| 139 | return 0; |
| 140 | udelay(ME_DELAY); |
| 141 | } |
| 142 | |
| 143 | printk(BIOS_ERR, "ME: failed to become ready\n"); |
| 144 | return -1; |
| 145 | } |
| 146 | |
| 147 | static void mei_reset(void) |
| 148 | { |
| 149 | struct mei_csr host; |
| 150 | |
| 151 | if (mei_wait_for_me_ready() < 0) |
| 152 | return; |
| 153 | |
| 154 | /* Reset host and ME circular buffers for next message */ |
| 155 | read_host_csr(&host); |
| 156 | host.reset = 1; |
| 157 | host.interrupt_generate = 1; |
| 158 | write_host_csr(&host); |
| 159 | |
| 160 | if (mei_wait_for_me_ready() < 0) |
| 161 | return; |
| 162 | |
| 163 | /* Re-init and indicate host is ready */ |
| 164 | read_host_csr(&host); |
| 165 | host.interrupt_generate = 1; |
| 166 | host.ready = 1; |
| 167 | host.reset = 0; |
| 168 | write_host_csr(&host); |
| 169 | } |
| 170 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 171 | static int mei_send_packet(struct mei_header *mei, void *req_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | { |
| 173 | struct mei_csr host; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 174 | unsigned int ndata, n; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 175 | u32 *data; |
| 176 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 177 | /* Number of dwords to write */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 178 | ndata = mei->length >> 2; |
| 179 | |
| 180 | /* Pad non-dword aligned request message length */ |
| 181 | if (mei->length & 3) |
| 182 | ndata++; |
| 183 | if (!ndata) { |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 184 | printk(BIOS_DEBUG, "ME: request has no data\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | return -1; |
| 186 | } |
| 187 | ndata++; /* Add MEI header */ |
| 188 | |
| 189 | /* |
| 190 | * Make sure there is still room left in the circular buffer. |
| 191 | * Reset the buffer pointers if the requested message will not fit. |
| 192 | */ |
| 193 | read_host_csr(&host); |
| 194 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 195 | printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); |
| 196 | mei_reset(); |
| 197 | read_host_csr(&host); |
| 198 | } |
| 199 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 200 | /* Ensure the requested length will fit in the circular buffer. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 201 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 202 | printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", |
| 203 | ndata + 2, host.buffer_depth); |
| 204 | return -1; |
| 205 | } |
| 206 | |
| 207 | /* Write MEI header */ |
| 208 | mei_write_dword_ptr(mei, MEI_H_CB_WW); |
| 209 | ndata--; |
| 210 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 211 | /* Write message data */ |
| 212 | data = req_data; |
| 213 | for (n = 0; n < ndata; ++n) |
| 214 | write_cb(*data++); |
| 215 | |
| 216 | /* Generate interrupt to the ME */ |
| 217 | read_host_csr(&host); |
| 218 | host.interrupt_generate = 1; |
| 219 | write_host_csr(&host); |
| 220 | |
| 221 | /* Make sure ME is ready after sending request data */ |
| 222 | return mei_wait_for_me_ready(); |
| 223 | } |
| 224 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 225 | static int mei_send_data(u8 me_address, u8 host_address, |
| 226 | void *req_data, int req_bytes) |
| 227 | { |
| 228 | struct mei_header header = { |
| 229 | .client_address = me_address, |
| 230 | .host_address = host_address, |
| 231 | }; |
| 232 | struct mei_csr host; |
| 233 | int current = 0; |
| 234 | u8 *req_ptr = req_data; |
| 235 | |
| 236 | while (!header.is_complete) { |
| 237 | int remain = req_bytes - current; |
| 238 | int buf_len; |
| 239 | |
| 240 | read_host_csr(&host); |
| 241 | buf_len = host.buffer_depth - host.buffer_write_ptr; |
| 242 | |
| 243 | if (buf_len > remain) { |
| 244 | /* Send all remaining data as final message */ |
| 245 | header.length = req_bytes - current; |
| 246 | header.is_complete = 1; |
| 247 | } else { |
| 248 | /* Send as much data as the buffer can hold */ |
| 249 | header.length = buf_len; |
| 250 | } |
| 251 | |
| 252 | mei_send_packet(&header, req_ptr); |
| 253 | |
| 254 | req_ptr += header.length; |
| 255 | current += header.length; |
| 256 | } |
| 257 | |
| 258 | return 0; |
| 259 | } |
| 260 | |
| 261 | static int mei_send_header(u8 me_address, u8 host_address, |
| 262 | void *header, int header_len, int complete) |
| 263 | { |
| 264 | struct mei_header mei = { |
| 265 | .client_address = me_address, |
| 266 | .host_address = host_address, |
| 267 | .length = header_len, |
| 268 | .is_complete = complete, |
| 269 | }; |
| 270 | return mei_send_packet(&mei, header); |
| 271 | } |
| 272 | |
| 273 | static int mei_recv_msg(void *header, int header_bytes, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 274 | void *rsp_data, int rsp_bytes) |
| 275 | { |
| 276 | struct mei_header mei_rsp; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 277 | struct mei_csr me, host; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 278 | unsigned int ndata, n; |
| 279 | unsigned int expected; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 280 | u32 *data; |
| 281 | |
| 282 | /* Total number of dwords to read from circular buffer */ |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 283 | expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 284 | if (rsp_bytes & 3) |
| 285 | expected++; |
| 286 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 287 | if (mei_wait_for_me_ready() < 0) |
| 288 | return -1; |
| 289 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 290 | /* |
| 291 | * The interrupt status bit does not appear to indicate that the |
| 292 | * message has actually been received. Instead we wait until the |
| 293 | * expected number of dwords are present in the circular buffer. |
| 294 | */ |
| 295 | for (n = ME_RETRY; n; --n) { |
| 296 | read_me_csr(&me); |
| 297 | if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) |
| 298 | break; |
| 299 | udelay(ME_DELAY); |
| 300 | } |
| 301 | if (!n) { |
| 302 | printk(BIOS_ERR, "ME: timeout waiting for data: expected " |
| 303 | "%u, available %u\n", expected, |
| 304 | me.buffer_write_ptr - me.buffer_read_ptr); |
| 305 | return -1; |
| 306 | } |
| 307 | |
| 308 | /* Read and verify MEI response header from the ME */ |
| 309 | mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); |
| 310 | if (!mei_rsp.is_complete) { |
| 311 | printk(BIOS_ERR, "ME: response is not complete\n"); |
| 312 | return -1; |
| 313 | } |
| 314 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 315 | /* Handle non-dword responses and expect at least the header */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 316 | ndata = mei_rsp.length >> 2; |
| 317 | if (mei_rsp.length & 3) |
| 318 | ndata++; |
| 319 | if (ndata != (expected - 1)) { |
| 320 | printk(BIOS_ERR, "ME: response is missing data %d != %d\n", |
| 321 | ndata, (expected - 1)); |
| 322 | return -1; |
| 323 | } |
| 324 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 325 | /* Read response header from the ME */ |
| 326 | data = header; |
| 327 | for (n = 0; n < (header_bytes >> 2); ++n) |
| 328 | *data++ = read_cb(); |
| 329 | ndata -= header_bytes >> 2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 330 | |
| 331 | /* Make sure caller passed a buffer with enough space */ |
| 332 | if (ndata != (rsp_bytes >> 2)) { |
| 333 | printk(BIOS_ERR, "ME: not enough room in response buffer: " |
| 334 | "%u != %u\n", ndata, rsp_bytes >> 2); |
| 335 | return -1; |
| 336 | } |
| 337 | |
| 338 | /* Read response data from the circular buffer */ |
| 339 | data = rsp_data; |
| 340 | for (n = 0; n < ndata; ++n) |
| 341 | *data++ = read_cb(); |
| 342 | |
| 343 | /* Tell the ME that we have consumed the response */ |
| 344 | read_host_csr(&host); |
| 345 | host.interrupt_status = 1; |
| 346 | host.interrupt_generate = 1; |
| 347 | write_host_csr(&host); |
| 348 | |
| 349 | return mei_wait_for_me_ready(); |
| 350 | } |
| 351 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 352 | static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, |
| 353 | void *req_data, int req_bytes, |
| 354 | void *rsp_data, int rsp_bytes) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 355 | { |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 356 | struct mkhi_header mkhi_rsp; |
| 357 | |
| 358 | /* Send header */ |
| 359 | if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 360 | mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 361 | return -1; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 362 | |
| 363 | /* Send data if available */ |
| 364 | if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 365 | req_data, req_bytes) < 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 366 | return -1; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 367 | |
| 368 | /* Return now if no response expected */ |
| 369 | if (!rsp_bytes) |
| 370 | return 0; |
| 371 | |
| 372 | /* Read header and data */ |
| 373 | if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), |
| 374 | rsp_data, rsp_bytes) < 0) |
| 375 | return -1; |
| 376 | |
| 377 | if (!mkhi_rsp.is_response || |
| 378 | mkhi->group_id != mkhi_rsp.group_id || |
| 379 | mkhi->command != mkhi_rsp.command) { |
| 380 | printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," |
| 381 | "command %u ?= %u, is_response %u\n", mkhi->group_id, |
| 382 | mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, |
| 383 | mkhi_rsp.is_response); |
| 384 | return -1; |
| 385 | } |
| 386 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 387 | return 0; |
| 388 | } |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 389 | |
Angel Pons | 7f8da79 | 2021-02-23 14:27:39 +0100 | [diff] [blame] | 390 | static inline int mei_sendrecv_icc(struct icc_header *icc, |
| 391 | void *req_data, int req_bytes, |
| 392 | void *rsp_data, int rsp_bytes) |
| 393 | { |
| 394 | struct icc_header icc_rsp; |
| 395 | |
| 396 | /* Send header */ |
| 397 | if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 398 | icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) |
| 399 | return -1; |
| 400 | |
| 401 | /* Send data if available */ |
| 402 | if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 403 | req_data, req_bytes) < 0) |
| 404 | return -1; |
| 405 | |
| 406 | /* Read header and data, if needed */ |
| 407 | if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), |
| 408 | rsp_data, rsp_bytes) < 0) |
| 409 | return -1; |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 414 | /* |
| 415 | * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read |
| 416 | * state machine on the BIOS end doesn't match the ME's state machine. |
| 417 | */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 418 | static void intel_me_mbp_give_up(struct device *dev) |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 419 | { |
| 420 | struct mei_csr csr; |
| 421 | |
| 422 | pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); |
| 423 | |
| 424 | read_host_csr(&csr); |
| 425 | csr.reset = 1; |
| 426 | csr.interrupt_generate = 1; |
| 427 | write_host_csr(&csr); |
| 428 | } |
| 429 | |
| 430 | /* |
| 431 | * mbp clear routine. This will wait for the ME to indicate that |
| 432 | * the MBP has been read and cleared. |
| 433 | */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 434 | static void intel_me_mbp_clear(struct device *dev) |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 435 | { |
| 436 | int count; |
| 437 | struct me_hfs2 hfs2; |
| 438 | |
| 439 | /* Wait for the mbp_cleared indicator */ |
| 440 | for (count = ME_RETRY; count > 0; --count) { |
| 441 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 442 | if (hfs2.mbp_cleared) |
| 443 | break; |
| 444 | udelay(ME_DELAY); |
| 445 | } |
| 446 | |
| 447 | if (count == 0) { |
| 448 | printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); |
| 449 | intel_me_mbp_give_up(dev); |
| 450 | } else { |
| 451 | printk(BIOS_INFO, "ME: MBP cleared\n"); |
| 452 | } |
| 453 | } |
| 454 | |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 455 | static void me_print_fw_version(mbp_fw_version_name *vers_name) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 456 | { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 457 | if (!vers_name) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 458 | printk(BIOS_ERR, "ME: mbp missing version report\n"); |
| 459 | return; |
| 460 | } |
| 461 | |
| 462 | printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", |
| 463 | vers_name->major_version, vers_name->minor_version, |
| 464 | vers_name->hotfix_version, vers_name->build_version); |
| 465 | } |
| 466 | |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 467 | static inline void print_cap(const char *name, int state) |
| 468 | { |
| 469 | printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", |
| 470 | name, state ? " en" : "dis"); |
| 471 | } |
| 472 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 473 | /* Get ME Firmware Capabilities */ |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 474 | static int mkhi_get_fwcaps(mbp_mefwcaps *cap) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 475 | { |
| 476 | u32 rule_id = 0; |
| 477 | struct me_fwcaps cap_msg; |
| 478 | struct mkhi_header mkhi = { |
| 479 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 480 | .command = MKHI_FWCAPS_GET_RULE, |
| 481 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 482 | |
| 483 | /* Send request and wait for response */ |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 484 | if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), |
| 485 | &cap_msg, sizeof(cap_msg)) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 486 | printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); |
| 487 | return -1; |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 488 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 489 | *cap = cap_msg.caps_sku; |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | /* Get ME Firmware Capabilities */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 494 | static void me_print_fwcaps(mbp_mefwcaps *cap) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 495 | { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 496 | mbp_mefwcaps local_caps; |
| 497 | if (!cap) { |
| 498 | cap = &local_caps; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 499 | printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); |
| 500 | if (mkhi_get_fwcaps(cap)) |
| 501 | return; |
| 502 | } |
| 503 | |
| 504 | print_cap("Full Network manageability", cap->full_net); |
| 505 | print_cap("Regular Network manageability", cap->std_net); |
| 506 | print_cap("Manageability", cap->manageability); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 507 | print_cap("IntelR Anti-Theft (AT)", cap->intel_at); |
| 508 | print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); |
| 509 | print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); |
| 510 | print_cap("ICC Over Clocking", cap->icc_over_clocking); |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 511 | print_cap("Protected Audio Video Path (PAVP)", cap->pavp); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 512 | print_cap("IPV6", cap->ipv6); |
| 513 | print_cap("KVM Remote Control (KVM)", cap->kvm); |
| 514 | print_cap("Outbreak Containment Heuristic (OCH)", cap->och); |
| 515 | print_cap("Virtual LAN (VLAN)", cap->vlan); |
| 516 | print_cap("TLS", cap->tls); |
| 517 | print_cap("Wireless LAN (WLAN)", cap->wlan); |
| 518 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 519 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 520 | /* Send END OF POST message to the ME */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 521 | static int mkhi_end_of_post(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 522 | { |
| 523 | struct mkhi_header mkhi = { |
| 524 | .group_id = MKHI_GROUP_ID_GEN, |
| 525 | .command = MKHI_END_OF_POST, |
| 526 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 527 | u32 eop_ack; |
| 528 | |
| 529 | /* Send request and wait for response */ |
Angel Pons | 08e8cab | 2020-06-18 15:20:37 +0200 | [diff] [blame] | 530 | printk(BIOS_NOTICE, "ME: %s\n", __func__); |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 531 | if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 532 | printk(BIOS_ERR, "ME: END OF POST message failed\n"); |
| 533 | return -1; |
| 534 | } |
| 535 | |
| 536 | printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); |
| 537 | return 0; |
| 538 | } |
| 539 | |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 540 | void intel_me_finalize(struct device *dev) |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 541 | { |
| 542 | struct me_hfs hfs; |
| 543 | u32 reg32; |
| 544 | |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 545 | reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 546 | mei_base_address = (u8 *)(uintptr_t)(reg32 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 547 | |
| 548 | /* S3 path will have hidden this device already */ |
Angel Pons | a3492d7 | 2021-02-23 14:12:25 +0100 | [diff] [blame] | 549 | if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0) |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 550 | return; |
| 551 | |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 552 | /* Wait for ME MBP Cleared indicator */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 553 | intel_me_mbp_clear(dev); |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 554 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 555 | /* Make sure ME is in a mode that expects EOP */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 556 | reg32 = pci_read_config32(dev, PCI_ME_HFS); |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 557 | memcpy(&hfs, ®32, sizeof(u32)); |
| 558 | |
| 559 | /* Abort and leave device alone if not normal mode */ |
| 560 | if (hfs.fpt_bad || |
| 561 | hfs.working_state != ME_HFS_CWS_NORMAL || |
| 562 | hfs.operation_mode != ME_HFS_MODE_NORMAL) |
| 563 | return; |
| 564 | |
| 565 | /* Try to send EOP command so ME stops accepting other commands */ |
| 566 | mkhi_end_of_post(); |
| 567 | |
| 568 | /* Make sure IO is disabled */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 569 | pci_and_config16(dev, PCI_COMMAND, |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 570 | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 571 | |
| 572 | /* Hide the PCI device */ |
| 573 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 574 | } |
| 575 | |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 576 | static int me_icc_set_clock_enables(u32 mask) |
| 577 | { |
| 578 | struct icc_clock_enables_msg clk = { |
| 579 | .clock_enables = 0, /* Turn off specified clocks */ |
| 580 | .clock_mask = mask, |
| 581 | .no_response = 1, /* Do not expect response */ |
| 582 | }; |
| 583 | struct icc_header icc = { |
| 584 | .api_version = ICC_API_VERSION_LYNXPOINT, |
| 585 | .icc_command = ICC_SET_CLOCK_ENABLES, |
| 586 | .length = sizeof(clk), |
| 587 | }; |
| 588 | |
| 589 | /* Send request and wait for response */ |
| 590 | if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { |
| 591 | printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); |
| 592 | return -1; |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 593 | } |
Elyes HAOUAS | 54f9424 | 2018-10-25 10:57:39 +0200 | [diff] [blame] | 594 | printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 595 | return 0; |
| 596 | } |
| 597 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 598 | /* Determine the path that we should take based on ME status */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 599 | static me_bios_path intel_me_path(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 600 | { |
| 601 | me_bios_path path = ME_DISABLE_BIOS_PATH; |
| 602 | struct me_hfs hfs; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 603 | struct me_hfs2 hfs2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 604 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 605 | pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 606 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 607 | |
| 608 | /* Check and dump status */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 609 | intel_me_status(&hfs, &hfs2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 610 | |
| 611 | /* Check Current Working State */ |
| 612 | switch (hfs.working_state) { |
| 613 | case ME_HFS_CWS_NORMAL: |
| 614 | path = ME_NORMAL_BIOS_PATH; |
| 615 | break; |
| 616 | case ME_HFS_CWS_REC: |
| 617 | path = ME_RECOVERY_BIOS_PATH; |
| 618 | break; |
| 619 | default: |
| 620 | path = ME_DISABLE_BIOS_PATH; |
| 621 | break; |
| 622 | } |
| 623 | |
| 624 | /* Check Current Operation Mode */ |
| 625 | switch (hfs.operation_mode) { |
| 626 | case ME_HFS_MODE_NORMAL: |
| 627 | break; |
| 628 | case ME_HFS_MODE_DEBUG: |
| 629 | case ME_HFS_MODE_DIS: |
| 630 | case ME_HFS_MODE_OVER_JMPR: |
| 631 | case ME_HFS_MODE_OVER_MEI: |
| 632 | default: |
| 633 | path = ME_DISABLE_BIOS_PATH; |
| 634 | break; |
| 635 | } |
| 636 | |
| 637 | /* Check for any error code and valid firmware and MBP */ |
| 638 | if (hfs.error_code || hfs.fpt_bad) |
| 639 | path = ME_ERROR_BIOS_PATH; |
| 640 | |
| 641 | /* Check if the MBP is ready */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 642 | if (!hfs2.mbp_rdy) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 643 | printk(BIOS_CRIT, "%s: mbp is not ready!\n", |
Angel Pons | 08e8cab | 2020-06-18 15:20:37 +0200 | [diff] [blame] | 644 | __func__); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 645 | path = ME_ERROR_BIOS_PATH; |
| 646 | } |
| 647 | |
Kyösti Mälkki | be5317f | 2019-11-06 12:07:21 +0200 | [diff] [blame] | 648 | if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 649 | struct elog_event_data_me_extended data = { |
| 650 | .current_working_state = hfs.working_state, |
| 651 | .operation_state = hfs.operation_state, |
| 652 | .operation_mode = hfs.operation_mode, |
| 653 | .error_code = hfs.error_code, |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 654 | .progress_code = hfs2.progress_code, |
| 655 | .current_pmevent = hfs2.current_pmevent, |
| 656 | .current_state = hfs2.current_state, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 657 | }; |
| 658 | elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); |
| 659 | elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, |
| 660 | &data, sizeof(data)); |
| 661 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 662 | |
| 663 | return path; |
| 664 | } |
| 665 | |
| 666 | /* Prepare ME for MEI messages */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 667 | static int intel_mei_setup(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 668 | { |
| 669 | struct resource *res; |
| 670 | struct mei_csr host; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 671 | |
| 672 | /* Find the MMIO base for the ME interface */ |
Angel Pons | f32ae10 | 2021-11-03 13:07:14 +0100 | [diff] [blame] | 673 | res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 674 | if (!res || res->base == 0 || res->size == 0) { |
| 675 | printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); |
| 676 | return -1; |
| 677 | } |
Angel Pons | d32b514 | 2021-02-23 14:23:49 +0100 | [diff] [blame] | 678 | mei_base_address = res2mmio(res, 0, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 679 | |
| 680 | /* Ensure Memory and Bus Master bits are set */ |
Angel Pons | d5d4fbc | 2020-05-31 01:03:59 +0200 | [diff] [blame] | 681 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 682 | |
| 683 | /* Clean up status for next message */ |
| 684 | read_host_csr(&host); |
| 685 | host.interrupt_generate = 1; |
| 686 | host.ready = 1; |
| 687 | host.reset = 0; |
| 688 | write_host_csr(&host); |
| 689 | |
| 690 | return 0; |
| 691 | } |
| 692 | |
| 693 | /* Read the Extend register hash of ME firmware */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 694 | static int intel_me_extend_valid(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 695 | { |
| 696 | struct me_heres status; |
| 697 | u32 extend[8] = {0}; |
| 698 | int i, count = 0; |
| 699 | |
| 700 | pci_read_dword_ptr(dev, &status, PCI_ME_HERES); |
| 701 | if (!status.extend_feature_present) { |
| 702 | printk(BIOS_ERR, "ME: Extend Feature not present\n"); |
| 703 | return -1; |
| 704 | } |
| 705 | |
| 706 | if (!status.extend_reg_valid) { |
| 707 | printk(BIOS_ERR, "ME: Extend Register not valid\n"); |
| 708 | return -1; |
| 709 | } |
| 710 | |
| 711 | switch (status.extend_reg_algorithm) { |
| 712 | case PCI_ME_EXT_SHA1: |
| 713 | count = 5; |
| 714 | printk(BIOS_DEBUG, "ME: Extend SHA-1: "); |
| 715 | break; |
| 716 | case PCI_ME_EXT_SHA256: |
| 717 | count = 8; |
| 718 | printk(BIOS_DEBUG, "ME: Extend SHA-256: "); |
| 719 | break; |
| 720 | default: |
| 721 | printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", |
| 722 | status.extend_reg_algorithm); |
| 723 | return -1; |
| 724 | } |
| 725 | |
| 726 | for (i = 0; i < count; ++i) { |
| 727 | extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); |
| 728 | printk(BIOS_DEBUG, "%08x", extend[i]); |
| 729 | } |
| 730 | printk(BIOS_DEBUG, "\n"); |
| 731 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 732 | /* Save hash in NVS for the OS to verify */ |
Kyösti Mälkki | 84d10cc | 2021-02-10 17:53:34 +0200 | [diff] [blame] | 733 | if (CONFIG(CHROMEOS_NVS)) |
Kyösti Mälkki | 26e0f4c | 2020-12-19 19:10:45 +0200 | [diff] [blame] | 734 | chromeos_set_me_hash(extend, count); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 739 | static u32 me_to_host_words_pending(void) |
| 740 | { |
| 741 | struct mei_csr me; |
| 742 | read_me_csr(&me); |
| 743 | if (!me.ready) |
| 744 | return 0; |
| 745 | return (me.buffer_write_ptr - me.buffer_read_ptr) & |
| 746 | (me.buffer_depth - 1); |
| 747 | } |
| 748 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 749 | struct mbp_payload { |
| 750 | mbp_header header; |
| 751 | u32 data[0]; |
| 752 | }; |
| 753 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 754 | /* |
Angel Pons | 7f8da79 | 2021-02-23 14:27:39 +0100 | [diff] [blame] | 755 | * Read and print ME MBP data |
| 756 | * |
| 757 | * Return -1 to indicate a problem (give up) |
| 758 | * Return 0 to indicate success (send LOCK+EOP) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 759 | */ |
Angel Pons | 10274d8 | 2021-02-23 14:19:28 +0100 | [diff] [blame] | 760 | static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 761 | { |
| 762 | mbp_header mbp_hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 763 | u32 me2host_pending; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 764 | struct mei_csr host; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 765 | struct me_hfs2 hfs2; |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 766 | struct mbp_payload *mbp; |
| 767 | int i; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 768 | |
| 769 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 770 | |
| 771 | if (!hfs2.mbp_rdy) { |
| 772 | printk(BIOS_ERR, "ME: MBP not ready\n"); |
| 773 | goto mbp_failure; |
| 774 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 775 | |
| 776 | me2host_pending = me_to_host_words_pending(); |
| 777 | if (!me2host_pending) { |
| 778 | printk(BIOS_ERR, "ME: no mbp data!\n"); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 779 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 780 | } |
| 781 | |
| 782 | /* we know for sure that at least the header is there */ |
| 783 | mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); |
| 784 | |
| 785 | if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || |
| 786 | (me2host_pending < mbp_hdr.mbp_size)) { |
| 787 | printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" |
| 788 | " buffer contains %d words\n", |
| 789 | mbp_hdr.num_entries, mbp_hdr.mbp_size, |
| 790 | me2host_pending); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 791 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 792 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 793 | mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); |
| 794 | if (!mbp) |
| 795 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 796 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 797 | mbp->header = mbp_hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 798 | me2host_pending--; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 799 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 800 | i = 0; |
| 801 | while (i != me2host_pending) { |
| 802 | mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); |
| 803 | i++; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 804 | } |
| 805 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 806 | /* Signal to the ME that the host has finished reading the MBP. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 807 | read_host_csr(&host); |
| 808 | host.interrupt_generate = 1; |
| 809 | write_host_csr(&host); |
| 810 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 811 | /* Dump out the MBP contents. */ |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 812 | if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { |
| 813 | printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", |
| 814 | mbp->header.num_entries, mbp->header.mbp_size); |
| 815 | if (CONFIG(DEBUG_INTEL_ME)) { |
| 816 | for (i = 0; i < mbp->header.mbp_size - 1; i++) { |
| 817 | printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); |
| 818 | } |
| 819 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 820 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 821 | |
| 822 | #define ASSIGN_FIELD_PTR(field_,val_) \ |
| 823 | { \ |
| 824 | mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ |
| 825 | break; \ |
| 826 | } |
| 827 | /* Setup the pointers in the me_bios_payload structure. */ |
| 828 | for (i = 0; i < mbp->header.mbp_size - 1;) { |
| 829 | mbp_item_header *item = (void *)&mbp->data[i]; |
| 830 | |
Elyes HAOUAS | f9de5a4 | 2018-05-03 17:21:02 +0200 | [diff] [blame] | 831 | switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 832 | case MBP_IDENT(KERNEL, FW_VER): |
| 833 | ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); |
| 834 | |
| 835 | case MBP_IDENT(ICC, PROFILE): |
| 836 | ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); |
| 837 | |
| 838 | case MBP_IDENT(INTEL_AT, STATE): |
| 839 | ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); |
| 840 | |
| 841 | case MBP_IDENT(KERNEL, FW_CAP): |
| 842 | ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); |
| 843 | |
| 844 | case MBP_IDENT(KERNEL, ROM_BIST): |
| 845 | ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); |
| 846 | |
| 847 | case MBP_IDENT(KERNEL, PLAT_KEY): |
| 848 | ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); |
| 849 | |
| 850 | case MBP_IDENT(KERNEL, FW_TYPE): |
| 851 | ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); |
| 852 | |
| 853 | case MBP_IDENT(KERNEL, MFS_FAILURE): |
| 854 | ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); |
| 855 | |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 856 | case MBP_IDENT(KERNEL, PLAT_TIME): |
| 857 | ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); |
| 858 | |
| 859 | case MBP_IDENT(NFC, SUPPORT_DATA): |
| 860 | ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); |
| 861 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 862 | default: |
Duncan Laurie | 0b3cd36 | 2013-08-08 15:40:01 -0700 | [diff] [blame] | 863 | printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " |
| 864 | "dw offset 0x%x\n", mbp->data[i], i); |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 865 | break; |
| 866 | } |
| 867 | i += item->length; |
| 868 | } |
| 869 | #undef ASSIGN_FIELD_PTR |
| 870 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 871 | return 0; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 872 | |
| 873 | mbp_failure: |
| 874 | intel_me_mbp_give_up(dev); |
| 875 | return -1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 876 | } |
Angel Pons | 7f8da79 | 2021-02-23 14:27:39 +0100 | [diff] [blame] | 877 | |
| 878 | /* Check whether ME is present and do basic init */ |
| 879 | static void intel_me_init(struct device *dev) |
| 880 | { |
| 881 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 882 | me_bios_path path = intel_me_path(dev); |
| 883 | me_bios_payload mbp_data; |
| 884 | |
| 885 | /* Do initial setup and determine the BIOS path */ |
| 886 | printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); |
| 887 | |
| 888 | if (path == ME_NORMAL_BIOS_PATH) { |
| 889 | /* Validate the extend register */ |
| 890 | intel_me_extend_valid(dev); |
| 891 | } |
| 892 | |
| 893 | memset(&mbp_data, 0, sizeof(mbp_data)); |
| 894 | |
| 895 | /* |
| 896 | * According to the ME9 BWG, BIOS is required to fetch MBP data in |
| 897 | * all boot flows except S3 Resume. |
| 898 | */ |
| 899 | |
| 900 | /* Prepare MEI MMIO interface */ |
| 901 | if (intel_mei_setup(dev) < 0) |
| 902 | return; |
| 903 | |
| 904 | if (intel_me_read_mbp(&mbp_data, dev)) |
| 905 | return; |
| 906 | |
| 907 | if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { |
| 908 | me_print_fw_version(mbp_data.fw_version_name); |
| 909 | |
| 910 | if (CONFIG(DEBUG_INTEL_ME)) |
| 911 | me_print_fwcaps(mbp_data.fw_capabilities); |
| 912 | |
| 913 | if (mbp_data.plat_time) { |
| 914 | printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", |
| 915 | mbp_data.plat_time->wake_event_mrst_time_ms); |
| 916 | printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", |
| 917 | mbp_data.plat_time->mrst_pltrst_time_ms); |
| 918 | printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", |
| 919 | mbp_data.plat_time->pltrst_cpurst_time_ms); |
| 920 | } |
| 921 | } |
| 922 | |
| 923 | /* Set clock enables according to devicetree */ |
| 924 | if (config && config->icc_clock_disable) |
| 925 | me_icc_set_clock_enables(config->icc_clock_disable); |
| 926 | |
| 927 | /* |
| 928 | * Leave the ME unlocked. It will be locked later. |
| 929 | */ |
| 930 | } |
| 931 | |
| 932 | static void intel_me_enable(struct device *dev) |
| 933 | { |
| 934 | /* Avoid talking to the device in S3 path */ |
| 935 | if (acpi_is_wakeup_s3()) { |
| 936 | dev->enabled = 0; |
| 937 | pch_disable_devfn(dev); |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | static struct device_operations device_ops = { |
| 942 | .read_resources = pci_dev_read_resources, |
| 943 | .set_resources = pci_dev_set_resources, |
| 944 | .enable_resources = pci_dev_enable_resources, |
| 945 | .enable = intel_me_enable, |
| 946 | .init = intel_me_init, |
| 947 | .final = intel_me_finalize, |
| 948 | .ops_pci = &pci_dev_ops_pci, |
| 949 | }; |
| 950 | |
| 951 | static const unsigned short pci_device_ids[] = { |
| 952 | PCI_DEVICE_ID_INTEL_LPT_H_MEI, |
| 953 | PCI_DEVICE_ID_INTEL_LPT_LP_MEI, |
| 954 | 0 |
| 955 | }; |
| 956 | |
| 957 | static const struct pci_driver intel_me __pci_driver = { |
| 958 | .ops = &device_ops, |
| 959 | .vendor = PCI_VENDOR_ID_INTEL, |
| 960 | .devices = pci_device_ids, |
| 961 | }; |