blob: cdae2713250cf98b78e7ee1eae97fc9ffe06bd35 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin76c37002012-10-30 09:03:43 -05002
3/*
4 * This is a ramstage driver for the Intel Management Engine found in the
5 * 6-series chipset. It handles the required boot-time messages over the
6 * MMIO-based Management Engine Interface to tell the ME that the BIOS is
7 * finished with POST. Additional messages are defined for debug but are
8 * not used unless the console loglevel is high enough.
9 */
10
Furquan Shaikh76cedd22020-05-02 10:24:23 -070011#include <acpi/acpi.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +020012#include <device/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020013#include <device/pci_ops.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050014#include <console/console.h>
Stefan Reinauer24d1d4b2013-03-21 11:51:41 -070015#include <device/device.h>
16#include <device/pci.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050017#include <device/pci_ids.h>
18#include <device/pci_def.h>
19#include <string.h>
20#include <delay.h>
21#include <elog.h>
Patrick Georgi546953c2014-11-29 10:38:17 +010022#include <halt.h>
Elyes HAOUAS400f9ca2019-06-23 07:01:22 +020023#include <stdlib.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050024
Kyösti Mälkki12b121c2019-08-18 16:33:39 +030025#include "chip.h"
Aaron Durbin76c37002012-10-30 09:03:43 -050026#include "me.h"
27#include "pch.h"
28
Julius Wernercd49cce2019-03-05 16:53:33 -080029#if CONFIG(CHROMEOS)
Aaron Durbin76c37002012-10-30 09:03:43 -050030#include <vendorcode/google/chromeos/chromeos.h>
31#include <vendorcode/google/chromeos/gnvs.h>
32#endif
33
Aaron Durbin76c37002012-10-30 09:03:43 -050034/* Path that the BIOS should take based on ME state */
Kyösti Mälkki21d6a272019-11-05 18:50:38 +020035static const char *me_bios_path_values[] __unused = {
Aaron Durbin76c37002012-10-30 09:03:43 -050036 [ME_NORMAL_BIOS_PATH] = "Normal",
37 [ME_S3WAKE_BIOS_PATH] = "S3 Wake",
38 [ME_ERROR_BIOS_PATH] = "Error",
39 [ME_RECOVERY_BIOS_PATH] = "Recovery",
40 [ME_DISABLE_BIOS_PATH] = "Disable",
41 [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
42};
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +010043static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
Aaron Durbin76c37002012-10-30 09:03:43 -050044
45/* MMIO base address for MEI interface */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080046static u32 *mei_base_address;
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +010047#ifdef __SIMPLE_DEVICE__
48void intel_me_mbp_clear(pci_devfn_t dev);
49#else
50void intel_me_mbp_clear(struct device *dev);
51#endif
Aaron Durbin76c37002012-10-30 09:03:43 -050052
Aaron Durbin76c37002012-10-30 09:03:43 -050053static void mei_dump(void *ptr, int dword, int offset, const char *type)
54{
55 struct mei_csr *csr;
56
Kyösti Mälkkic86fc8e2019-11-06 06:32:27 +020057 if (!CONFIG(DEBUG_INTEL_ME))
58 return;
59
Aaron Durbin76c37002012-10-30 09:03:43 -050060 printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
61
62 switch (offset) {
63 case MEI_H_CSR:
64 case MEI_ME_CSR_HA:
65 csr = ptr;
66 if (!csr) {
67 printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
68 break;
69 }
70 printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
71 "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
72 csr->buffer_read_ptr, csr->buffer_write_ptr,
73 csr->ready, csr->reset, csr->interrupt_generate,
74 csr->interrupt_status, csr->interrupt_enable);
75 break;
76 case MEI_ME_CB_RW:
77 case MEI_H_CB_WW:
78 printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
79 break;
80 default:
81 printk(BIOS_SPEW, "0x%08x\n", offset);
82 break;
83 }
84}
Aaron Durbin76c37002012-10-30 09:03:43 -050085
86/*
87 * ME/MEI access helpers using memcpy to avoid aliasing.
88 */
89
90static inline void mei_read_dword_ptr(void *ptr, int offset)
91{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080092 u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
Aaron Durbin76c37002012-10-30 09:03:43 -050093 memcpy(ptr, &dword, sizeof(dword));
94 mei_dump(ptr, dword, offset, "READ");
95}
96
97static inline void mei_write_dword_ptr(void *ptr, int offset)
98{
99 u32 dword = 0;
100 memcpy(&dword, ptr, sizeof(dword));
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800101 write32(mei_base_address + (offset/sizeof(u32)), dword);
Aaron Durbin76c37002012-10-30 09:03:43 -0500102 mei_dump(ptr, dword, offset, "WRITE");
103}
104
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100105#ifdef __SIMPLE_DEVICE__
106static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset)
107#else
108static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
109#endif
Aaron Durbin76c37002012-10-30 09:03:43 -0500110{
111 u32 dword = pci_read_config32(dev, offset);
112 memcpy(ptr, &dword, sizeof(dword));
113 mei_dump(ptr, dword, offset, "PCI READ");
114}
Aaron Durbin76c37002012-10-30 09:03:43 -0500115
116static inline void read_host_csr(struct mei_csr *csr)
117{
118 mei_read_dword_ptr(csr, MEI_H_CSR);
119}
120
121static inline void write_host_csr(struct mei_csr *csr)
122{
123 mei_write_dword_ptr(csr, MEI_H_CSR);
124}
125
126static inline void read_me_csr(struct mei_csr *csr)
127{
128 mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
129}
130
131static inline void write_cb(u32 dword)
132{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800133 write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
Aaron Durbin76c37002012-10-30 09:03:43 -0500134 mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
135}
136
137static inline u32 read_cb(void)
138{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800139 u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
Aaron Durbin76c37002012-10-30 09:03:43 -0500140 mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
141 return dword;
142}
143
144/* Wait for ME ready bit to be asserted */
145static int mei_wait_for_me_ready(void)
146{
147 struct mei_csr me;
Martin Rothff744bf2019-10-23 21:46:03 -0600148 unsigned int try = ME_RETRY;
Aaron Durbin76c37002012-10-30 09:03:43 -0500149
150 while (try--) {
151 read_me_csr(&me);
152 if (me.ready)
153 return 0;
154 udelay(ME_DELAY);
155 }
156
157 printk(BIOS_ERR, "ME: failed to become ready\n");
158 return -1;
159}
160
161static void mei_reset(void)
162{
163 struct mei_csr host;
164
165 if (mei_wait_for_me_ready() < 0)
166 return;
167
168 /* Reset host and ME circular buffers for next message */
169 read_host_csr(&host);
170 host.reset = 1;
171 host.interrupt_generate = 1;
172 write_host_csr(&host);
173
174 if (mei_wait_for_me_ready() < 0)
175 return;
176
177 /* Re-init and indicate host is ready */
178 read_host_csr(&host);
179 host.interrupt_generate = 1;
180 host.ready = 1;
181 host.reset = 0;
182 write_host_csr(&host);
183}
184
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700185static int mei_send_packet(struct mei_header *mei, void *req_data)
Aaron Durbin76c37002012-10-30 09:03:43 -0500186{
187 struct mei_csr host;
Martin Rothff744bf2019-10-23 21:46:03 -0600188 unsigned int ndata, n;
Aaron Durbin76c37002012-10-30 09:03:43 -0500189 u32 *data;
190
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700191 /* Number of dwords to write */
Aaron Durbin76c37002012-10-30 09:03:43 -0500192 ndata = mei->length >> 2;
193
194 /* Pad non-dword aligned request message length */
195 if (mei->length & 3)
196 ndata++;
197 if (!ndata) {
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700198 printk(BIOS_DEBUG, "ME: request has no data\n");
Aaron Durbin76c37002012-10-30 09:03:43 -0500199 return -1;
200 }
201 ndata++; /* Add MEI header */
202
203 /*
204 * Make sure there is still room left in the circular buffer.
205 * Reset the buffer pointers if the requested message will not fit.
206 */
207 read_host_csr(&host);
208 if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
209 printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
210 mei_reset();
211 read_host_csr(&host);
212 }
213
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700214 /* Ensure the requested length will fit in the circular buffer. */
Aaron Durbin76c37002012-10-30 09:03:43 -0500215 if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
216 printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
217 ndata + 2, host.buffer_depth);
218 return -1;
219 }
220
221 /* Write MEI header */
222 mei_write_dword_ptr(mei, MEI_H_CB_WW);
223 ndata--;
224
Aaron Durbin76c37002012-10-30 09:03:43 -0500225 /* Write message data */
226 data = req_data;
227 for (n = 0; n < ndata; ++n)
228 write_cb(*data++);
229
230 /* Generate interrupt to the ME */
231 read_host_csr(&host);
232 host.interrupt_generate = 1;
233 write_host_csr(&host);
234
235 /* Make sure ME is ready after sending request data */
236 return mei_wait_for_me_ready();
237}
238
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700239static int mei_send_data(u8 me_address, u8 host_address,
240 void *req_data, int req_bytes)
241{
242 struct mei_header header = {
243 .client_address = me_address,
244 .host_address = host_address,
245 };
246 struct mei_csr host;
247 int current = 0;
248 u8 *req_ptr = req_data;
249
250 while (!header.is_complete) {
251 int remain = req_bytes - current;
252 int buf_len;
253
254 read_host_csr(&host);
255 buf_len = host.buffer_depth - host.buffer_write_ptr;
256
257 if (buf_len > remain) {
258 /* Send all remaining data as final message */
259 header.length = req_bytes - current;
260 header.is_complete = 1;
261 } else {
262 /* Send as much data as the buffer can hold */
263 header.length = buf_len;
264 }
265
266 mei_send_packet(&header, req_ptr);
267
268 req_ptr += header.length;
269 current += header.length;
270 }
271
272 return 0;
273}
274
275static int mei_send_header(u8 me_address, u8 host_address,
276 void *header, int header_len, int complete)
277{
278 struct mei_header mei = {
279 .client_address = me_address,
280 .host_address = host_address,
281 .length = header_len,
282 .is_complete = complete,
283 };
284 return mei_send_packet(&mei, header);
285}
286
287static int mei_recv_msg(void *header, int header_bytes,
Aaron Durbin76c37002012-10-30 09:03:43 -0500288 void *rsp_data, int rsp_bytes)
289{
290 struct mei_header mei_rsp;
Aaron Durbin76c37002012-10-30 09:03:43 -0500291 struct mei_csr me, host;
Martin Rothff744bf2019-10-23 21:46:03 -0600292 unsigned int ndata, n;
293 unsigned int expected;
Aaron Durbin76c37002012-10-30 09:03:43 -0500294 u32 *data;
295
296 /* Total number of dwords to read from circular buffer */
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700297 expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2;
Aaron Durbin76c37002012-10-30 09:03:43 -0500298 if (rsp_bytes & 3)
299 expected++;
300
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700301 if (mei_wait_for_me_ready() < 0)
302 return -1;
303
Aaron Durbin76c37002012-10-30 09:03:43 -0500304 /*
305 * The interrupt status bit does not appear to indicate that the
306 * message has actually been received. Instead we wait until the
307 * expected number of dwords are present in the circular buffer.
308 */
309 for (n = ME_RETRY; n; --n) {
310 read_me_csr(&me);
311 if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
312 break;
313 udelay(ME_DELAY);
314 }
315 if (!n) {
316 printk(BIOS_ERR, "ME: timeout waiting for data: expected "
317 "%u, available %u\n", expected,
318 me.buffer_write_ptr - me.buffer_read_ptr);
319 return -1;
320 }
321
322 /* Read and verify MEI response header from the ME */
323 mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
324 if (!mei_rsp.is_complete) {
325 printk(BIOS_ERR, "ME: response is not complete\n");
326 return -1;
327 }
328
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700329 /* Handle non-dword responses and expect at least the header */
Aaron Durbin76c37002012-10-30 09:03:43 -0500330 ndata = mei_rsp.length >> 2;
331 if (mei_rsp.length & 3)
332 ndata++;
333 if (ndata != (expected - 1)) {
334 printk(BIOS_ERR, "ME: response is missing data %d != %d\n",
335 ndata, (expected - 1));
336 return -1;
337 }
338
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700339 /* Read response header from the ME */
340 data = header;
341 for (n = 0; n < (header_bytes >> 2); ++n)
342 *data++ = read_cb();
343 ndata -= header_bytes >> 2;
Aaron Durbin76c37002012-10-30 09:03:43 -0500344
345 /* Make sure caller passed a buffer with enough space */
346 if (ndata != (rsp_bytes >> 2)) {
347 printk(BIOS_ERR, "ME: not enough room in response buffer: "
348 "%u != %u\n", ndata, rsp_bytes >> 2);
349 return -1;
350 }
351
352 /* Read response data from the circular buffer */
353 data = rsp_data;
354 for (n = 0; n < ndata; ++n)
355 *data++ = read_cb();
356
357 /* Tell the ME that we have consumed the response */
358 read_host_csr(&host);
359 host.interrupt_status = 1;
360 host.interrupt_generate = 1;
361 write_host_csr(&host);
362
363 return mei_wait_for_me_ready();
364}
365
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700366static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
367 void *req_data, int req_bytes,
368 void *rsp_data, int rsp_bytes)
Aaron Durbin76c37002012-10-30 09:03:43 -0500369{
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700370 struct mkhi_header mkhi_rsp;
371
372 /* Send header */
373 if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS,
374 mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0)
Aaron Durbin76c37002012-10-30 09:03:43 -0500375 return -1;
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700376
377 /* Send data if available */
378 if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS,
379 req_data, req_bytes) < 0)
Aaron Durbin76c37002012-10-30 09:03:43 -0500380 return -1;
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700381
382 /* Return now if no response expected */
383 if (!rsp_bytes)
384 return 0;
385
386 /* Read header and data */
387 if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp),
388 rsp_data, rsp_bytes) < 0)
389 return -1;
390
391 if (!mkhi_rsp.is_response ||
392 mkhi->group_id != mkhi_rsp.group_id ||
393 mkhi->command != mkhi_rsp.command) {
394 printk(BIOS_ERR, "ME: invalid response, group %u ?= %u,"
395 "command %u ?= %u, is_response %u\n", mkhi->group_id,
396 mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
397 mkhi_rsp.is_response);
398 return -1;
399 }
400
Aaron Durbin76c37002012-10-30 09:03:43 -0500401 return 0;
402}
Duncan Laurie0dc0d132013-08-08 15:31:51 -0700403
Duncan Laurie3d299c42013-07-19 08:48:05 -0700404/*
405 * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
406 * state machine on the BIOS end doesn't match the ME's state machine.
407 */
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100408#ifdef __SIMPLE_DEVICE__
409static void intel_me_mbp_give_up(pci_devfn_t dev)
410#else
411static void intel_me_mbp_give_up(struct device *dev)
412#endif
Duncan Laurie3d299c42013-07-19 08:48:05 -0700413{
414 struct mei_csr csr;
415
416 pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP);
417
418 read_host_csr(&csr);
419 csr.reset = 1;
420 csr.interrupt_generate = 1;
421 write_host_csr(&csr);
422}
423
424/*
425 * mbp clear routine. This will wait for the ME to indicate that
426 * the MBP has been read and cleared.
427 */
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100428#ifdef __SIMPLE_DEVICE__
429void intel_me_mbp_clear(pci_devfn_t dev)
430#else
431void intel_me_mbp_clear(struct device *dev)
432#endif
Duncan Laurie3d299c42013-07-19 08:48:05 -0700433{
434 int count;
435 struct me_hfs2 hfs2;
436
437 /* Wait for the mbp_cleared indicator */
438 for (count = ME_RETRY; count > 0; --count) {
439 pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
440 if (hfs2.mbp_cleared)
441 break;
442 udelay(ME_DELAY);
443 }
444
445 if (count == 0) {
446 printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n");
447 intel_me_mbp_give_up(dev);
448 } else {
449 printk(BIOS_INFO, "ME: MBP cleared\n");
450 }
451}
452
Kyösti Mälkkic86fc8e2019-11-06 06:32:27 +0200453static void __unused me_print_fw_version(mbp_fw_version_name *vers_name)
Aaron Durbin76c37002012-10-30 09:03:43 -0500454{
Aaron Durbinbe985242012-12-12 12:40:33 -0600455 if (!vers_name) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500456 printk(BIOS_ERR, "ME: mbp missing version report\n");
457 return;
458 }
459
460 printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n",
461 vers_name->major_version, vers_name->minor_version,
462 vers_name->hotfix_version, vers_name->build_version);
463}
464
Edward O'Callaghan7bf4f482014-06-17 15:12:09 +1000465static inline void print_cap(const char *name, int state)
466{
467 printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
468 name, state ? " en" : "dis");
469}
470
Aaron Durbin76c37002012-10-30 09:03:43 -0500471/* Get ME Firmware Capabilities */
Aaron Durbinbe985242012-12-12 12:40:33 -0600472static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
Aaron Durbin76c37002012-10-30 09:03:43 -0500473{
474 u32 rule_id = 0;
475 struct me_fwcaps cap_msg;
476 struct mkhi_header mkhi = {
477 .group_id = MKHI_GROUP_ID_FWCAPS,
478 .command = MKHI_FWCAPS_GET_RULE,
479 };
Aaron Durbin76c37002012-10-30 09:03:43 -0500480
481 /* Send request and wait for response */
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700482 if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32),
483 &cap_msg, sizeof(cap_msg)) < 0) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500484 printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
485 return -1;
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200486 }
Aaron Durbin76c37002012-10-30 09:03:43 -0500487 *cap = cap_msg.caps_sku;
488 return 0;
489}
490
491/* Get ME Firmware Capabilities */
Kyösti Mälkkic86fc8e2019-11-06 06:32:27 +0200492static void __unused me_print_fwcaps(mbp_mefwcaps *cap)
Aaron Durbin76c37002012-10-30 09:03:43 -0500493{
Aaron Durbinbe985242012-12-12 12:40:33 -0600494 mbp_mefwcaps local_caps;
495 if (!cap) {
496 cap = &local_caps;
Aaron Durbin76c37002012-10-30 09:03:43 -0500497 printk(BIOS_ERR, "ME: mbp missing fwcaps report\n");
498 if (mkhi_get_fwcaps(cap))
499 return;
500 }
501
502 print_cap("Full Network manageability", cap->full_net);
503 print_cap("Regular Network manageability", cap->std_net);
504 print_cap("Manageability", cap->manageability);
Aaron Durbin76c37002012-10-30 09:03:43 -0500505 print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
506 print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
507 print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
508 print_cap("ICC Over Clocking", cap->icc_over_clocking);
Edward O'Callaghan7bf4f482014-06-17 15:12:09 +1000509 print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
Aaron Durbin76c37002012-10-30 09:03:43 -0500510 print_cap("IPV6", cap->ipv6);
511 print_cap("KVM Remote Control (KVM)", cap->kvm);
512 print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
513 print_cap("Virtual LAN (VLAN)", cap->vlan);
514 print_cap("TLS", cap->tls);
515 print_cap("Wireless LAN (WLAN)", cap->wlan);
516}
Aaron Durbin76c37002012-10-30 09:03:43 -0500517
Julius Wernercd49cce2019-03-05 16:53:33 -0800518#if CONFIG(CHROMEOS) && 0 /* DISABLED */
Aaron Durbin76c37002012-10-30 09:03:43 -0500519/* Tell ME to issue a global reset */
520static int mkhi_global_reset(void)
521{
522 struct me_global_reset reset = {
523 .request_origin = GLOBAL_RESET_BIOS_POST,
524 .reset_type = CBM_RR_GLOBAL_RESET,
525 };
526 struct mkhi_header mkhi = {
527 .group_id = MKHI_GROUP_ID_CBM,
528 .command = MKHI_GLOBAL_RESET,
529 };
Aaron Durbin76c37002012-10-30 09:03:43 -0500530
531 /* Send request and wait for response */
Angel Pons08e8cab2020-06-18 15:20:37 +0200532 printk(BIOS_NOTICE, "ME: %s\n", __func__);
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700533 if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500534 /* No response means reset will happen shortly... */
Patrick Georgi546953c2014-11-29 10:38:17 +0100535 halt();
Aaron Durbin76c37002012-10-30 09:03:43 -0500536 }
537
538 /* If the ME responded it rejected the reset request */
539 printk(BIOS_ERR, "ME: Global Reset failed\n");
540 return -1;
541}
542#endif
543
Aaron Durbin76c37002012-10-30 09:03:43 -0500544/* Send END OF POST message to the ME */
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200545static int __unused mkhi_end_of_post(void)
Aaron Durbin76c37002012-10-30 09:03:43 -0500546{
547 struct mkhi_header mkhi = {
548 .group_id = MKHI_GROUP_ID_GEN,
549 .command = MKHI_END_OF_POST,
550 };
Aaron Durbin76c37002012-10-30 09:03:43 -0500551 u32 eop_ack;
552
553 /* Send request and wait for response */
Angel Pons08e8cab2020-06-18 15:20:37 +0200554 printk(BIOS_NOTICE, "ME: %s\n", __func__);
Duncan Laurie2017b4a2013-08-08 15:07:12 -0700555 if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500556 printk(BIOS_ERR, "ME: END OF POST message failed\n");
557 return -1;
558 }
559
560 printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack);
561 return 0;
562}
563
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200564#ifdef __SIMPLE_DEVICE__
565
Duncan Laurieaf980622013-07-18 23:02:18 -0700566void intel_me_finalize_smm(void)
567{
568 struct me_hfs hfs;
569 u32 reg32;
Elyes HAOUAS73ae0762020-04-28 10:13:05 +0200570 u16 reg16;
Duncan Laurieaf980622013-07-18 23:02:18 -0700571
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800572 mei_base_address = (u32 *)
573 (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
Duncan Laurieaf980622013-07-18 23:02:18 -0700574
575 /* S3 path will have hidden this device already */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800576 if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
Duncan Laurieaf980622013-07-18 23:02:18 -0700577 return;
578
Julius Wernercd49cce2019-03-05 16:53:33 -0800579#if CONFIG(ME_MBP_CLEAR_LATE)
Duncan Laurie3d299c42013-07-19 08:48:05 -0700580 /* Wait for ME MBP Cleared indicator */
581 intel_me_mbp_clear(PCH_ME_DEV);
582#endif
583
Duncan Laurieaf980622013-07-18 23:02:18 -0700584 /* Make sure ME is in a mode that expects EOP */
585 reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
586 memcpy(&hfs, &reg32, sizeof(u32));
587
588 /* Abort and leave device alone if not normal mode */
589 if (hfs.fpt_bad ||
590 hfs.working_state != ME_HFS_CWS_NORMAL ||
591 hfs.operation_mode != ME_HFS_MODE_NORMAL)
592 return;
593
594 /* Try to send EOP command so ME stops accepting other commands */
595 mkhi_end_of_post();
596
597 /* Make sure IO is disabled */
Elyes HAOUAS73ae0762020-04-28 10:13:05 +0200598 reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
599 reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
600 pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
Duncan Laurieaf980622013-07-18 23:02:18 -0700601
602 /* Hide the PCI device */
603 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
604}
605
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200606#else /* !__SIMPLE_DEVICE__ */
Duncan Laurieaf980622013-07-18 23:02:18 -0700607
Edward O'Callaghan97ccefd2015-01-07 15:53:00 +1100608static inline int mei_sendrecv_icc(struct icc_header *icc,
609 void *req_data, int req_bytes,
610 void *rsp_data, int rsp_bytes)
611{
612 struct icc_header icc_rsp;
613
614 /* Send header */
615 if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
616 icc, sizeof(*icc), req_bytes ? 0 : 1) < 0)
617 return -1;
618
619 /* Send data if available */
620 if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
621 req_data, req_bytes) < 0)
622 return -1;
623
624 /* Read header and data, if needed */
625 if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp),
626 rsp_data, rsp_bytes) < 0)
627 return -1;
628
629 return 0;
630}
631
Duncan Laurie0dc0d132013-08-08 15:31:51 -0700632static int me_icc_set_clock_enables(u32 mask)
633{
634 struct icc_clock_enables_msg clk = {
635 .clock_enables = 0, /* Turn off specified clocks */
636 .clock_mask = mask,
637 .no_response = 1, /* Do not expect response */
638 };
639 struct icc_header icc = {
640 .api_version = ICC_API_VERSION_LYNXPOINT,
641 .icc_command = ICC_SET_CLOCK_ENABLES,
642 .length = sizeof(clk),
643 };
644
645 /* Send request and wait for response */
646 if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
647 printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
648 return -1;
Duncan Laurie0dc0d132013-08-08 15:31:51 -0700649 }
650
Elyes HAOUAS54f94242018-10-25 10:57:39 +0200651 printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
Duncan Laurie0dc0d132013-08-08 15:31:51 -0700652 return 0;
653}
654
Aaron Durbin76c37002012-10-30 09:03:43 -0500655/* Determine the path that we should take based on ME status */
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100656static me_bios_path intel_me_path(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500657{
658 me_bios_path path = ME_DISABLE_BIOS_PATH;
659 struct me_hfs hfs;
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500660 struct me_hfs2 hfs2;
Aaron Durbin76c37002012-10-30 09:03:43 -0500661
Aaron Durbin76c37002012-10-30 09:03:43 -0500662 pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500663 pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
Aaron Durbin76c37002012-10-30 09:03:43 -0500664
665 /* Check and dump status */
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500666 intel_me_status(&hfs, &hfs2);
Aaron Durbin76c37002012-10-30 09:03:43 -0500667
668 /* Check Current Working State */
669 switch (hfs.working_state) {
670 case ME_HFS_CWS_NORMAL:
671 path = ME_NORMAL_BIOS_PATH;
672 break;
673 case ME_HFS_CWS_REC:
674 path = ME_RECOVERY_BIOS_PATH;
675 break;
676 default:
677 path = ME_DISABLE_BIOS_PATH;
678 break;
679 }
680
681 /* Check Current Operation Mode */
682 switch (hfs.operation_mode) {
683 case ME_HFS_MODE_NORMAL:
684 break;
685 case ME_HFS_MODE_DEBUG:
686 case ME_HFS_MODE_DIS:
687 case ME_HFS_MODE_OVER_JMPR:
688 case ME_HFS_MODE_OVER_MEI:
689 default:
690 path = ME_DISABLE_BIOS_PATH;
691 break;
692 }
693
694 /* Check for any error code and valid firmware and MBP */
695 if (hfs.error_code || hfs.fpt_bad)
696 path = ME_ERROR_BIOS_PATH;
697
698 /* Check if the MBP is ready */
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500699 if (!hfs2.mbp_rdy) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500700 printk(BIOS_CRIT, "%s: mbp is not ready!\n",
Angel Pons08e8cab2020-06-18 15:20:37 +0200701 __func__);
Aaron Durbin76c37002012-10-30 09:03:43 -0500702 path = ME_ERROR_BIOS_PATH;
703 }
704
Kyösti Mälkkibe5317f2019-11-06 12:07:21 +0200705 if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500706 struct elog_event_data_me_extended data = {
707 .current_working_state = hfs.working_state,
708 .operation_state = hfs.operation_state,
709 .operation_mode = hfs.operation_mode,
710 .error_code = hfs.error_code,
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500711 .progress_code = hfs2.progress_code,
712 .current_pmevent = hfs2.current_pmevent,
713 .current_state = hfs2.current_state,
Aaron Durbin76c37002012-10-30 09:03:43 -0500714 };
715 elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
716 elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
717 &data, sizeof(data));
718 }
Aaron Durbin76c37002012-10-30 09:03:43 -0500719
720 return path;
721}
722
723/* Prepare ME for MEI messages */
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100724static int intel_mei_setup(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500725{
726 struct resource *res;
727 struct mei_csr host;
Aaron Durbin76c37002012-10-30 09:03:43 -0500728
729 /* Find the MMIO base for the ME interface */
730 res = find_resource(dev, PCI_BASE_ADDRESS_0);
731 if (!res || res->base == 0 || res->size == 0) {
732 printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
733 return -1;
734 }
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800735 mei_base_address = (u32 *)(uintptr_t)res->base;
Aaron Durbin76c37002012-10-30 09:03:43 -0500736
737 /* Ensure Memory and Bus Master bits are set */
Angel Ponsd5d4fbc2020-05-31 01:03:59 +0200738 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
Aaron Durbin76c37002012-10-30 09:03:43 -0500739
740 /* Clean up status for next message */
741 read_host_csr(&host);
742 host.interrupt_generate = 1;
743 host.ready = 1;
744 host.reset = 0;
745 write_host_csr(&host);
746
747 return 0;
748}
749
750/* Read the Extend register hash of ME firmware */
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100751static int intel_me_extend_valid(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500752{
753 struct me_heres status;
754 u32 extend[8] = {0};
755 int i, count = 0;
756
757 pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
758 if (!status.extend_feature_present) {
759 printk(BIOS_ERR, "ME: Extend Feature not present\n");
760 return -1;
761 }
762
763 if (!status.extend_reg_valid) {
764 printk(BIOS_ERR, "ME: Extend Register not valid\n");
765 return -1;
766 }
767
768 switch (status.extend_reg_algorithm) {
769 case PCI_ME_EXT_SHA1:
770 count = 5;
771 printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
772 break;
773 case PCI_ME_EXT_SHA256:
774 count = 8;
775 printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
776 break;
777 default:
778 printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
779 status.extend_reg_algorithm);
780 return -1;
781 }
782
783 for (i = 0; i < count; ++i) {
784 extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
785 printk(BIOS_DEBUG, "%08x", extend[i]);
786 }
787 printk(BIOS_DEBUG, "\n");
788
Julius Wernercd49cce2019-03-05 16:53:33 -0800789#if CONFIG(CHROMEOS)
Aaron Durbin76c37002012-10-30 09:03:43 -0500790 /* Save hash in NVS for the OS to verify */
791 chromeos_set_me_hash(extend, count);
792#endif
793
794 return 0;
795}
796
Aaron Durbin76c37002012-10-30 09:03:43 -0500797/* Check whether ME is present and do basic init */
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100798static void intel_me_init(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500799{
Duncan Laurie0dc0d132013-08-08 15:31:51 -0700800 struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
Aaron Durbin76c37002012-10-30 09:03:43 -0500801 me_bios_path path = intel_me_path(dev);
802 me_bios_payload mbp_data;
803
804 /* Do initial setup and determine the BIOS path */
805 printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
806
Duncan Laurie8056dc62013-07-22 08:47:43 -0700807 if (path == ME_NORMAL_BIOS_PATH) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500808 /* Validate the extend register */
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500809 intel_me_extend_valid(dev);
810 }
Aaron Durbin76c37002012-10-30 09:03:43 -0500811
Aaron Durbinbe985242012-12-12 12:40:33 -0600812 memset(&mbp_data, 0, sizeof(mbp_data));
813
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500814 /*
815 * According to the ME9 BWG, BIOS is required to fetch MBP data in
816 * all boot flows except S3 Resume.
817 */
Aaron Durbin76c37002012-10-30 09:03:43 -0500818
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500819 /* Prepare MEI MMIO interface */
820 if (intel_mei_setup(dev) < 0)
821 return;
Aaron Durbin76c37002012-10-30 09:03:43 -0500822
Duncan Laurie144f7b22013-05-01 11:27:58 -0700823 if (intel_me_read_mbp(&mbp_data, dev))
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500824 return;
Aaron Durbin76c37002012-10-30 09:03:43 -0500825
Kyösti Mälkkic86fc8e2019-11-06 06:32:27 +0200826 if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) {
827 me_print_fw_version(mbp_data.fw_version_name);
Duncan Laurie144f7b22013-05-01 11:27:58 -0700828
Kyösti Mälkkic86fc8e2019-11-06 06:32:27 +0200829 if (CONFIG(DEBUG_INTEL_ME))
830 me_print_fwcaps(mbp_data.fw_capabilities);
831
832 if (mbp_data.plat_time) {
833 printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n",
834 mbp_data.plat_time->wake_event_mrst_time_ms);
835 printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n",
836 mbp_data.plat_time->mrst_pltrst_time_ms);
837 printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n",
838 mbp_data.plat_time->pltrst_cpurst_time_ms);
839 }
Duncan Laurie144f7b22013-05-01 11:27:58 -0700840 }
Aaron Durbin76c37002012-10-30 09:03:43 -0500841
Duncan Laurie0dc0d132013-08-08 15:31:51 -0700842 /* Set clock enables according to devicetree */
843 if (config && config->icc_clock_disable)
844 me_icc_set_clock_enables(config->icc_clock_disable);
845
Duncan Laurieaf980622013-07-18 23:02:18 -0700846 /*
847 * Leave the ME unlocked. It will be locked via SMI command later.
848 */
Aaron Durbin76c37002012-10-30 09:03:43 -0500849}
850
Elyes HAOUAS1dcd8db2018-12-05 10:59:42 +0100851static void intel_me_enable(struct device *dev)
Duncan Laurie8056dc62013-07-22 08:47:43 -0700852{
Duncan Laurie8056dc62013-07-22 08:47:43 -0700853 /* Avoid talking to the device in S3 path */
Kyösti Mälkkic3ed8862014-06-19 19:50:51 +0300854 if (acpi_is_wakeup_s3()) {
Duncan Laurie8056dc62013-07-22 08:47:43 -0700855 dev->enabled = 0;
856 pch_disable_devfn(dev);
857 }
Duncan Laurie8056dc62013-07-22 08:47:43 -0700858}
859
Aaron Durbin76c37002012-10-30 09:03:43 -0500860static struct device_operations device_ops = {
861 .read_resources = pci_dev_read_resources,
862 .set_resources = pci_dev_set_resources,
863 .enable_resources = pci_dev_enable_resources,
Duncan Laurie8056dc62013-07-22 08:47:43 -0700864 .enable = intel_me_enable,
Aaron Durbin76c37002012-10-30 09:03:43 -0500865 .init = intel_me_init,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200866 .ops_pci = &pci_dev_ops_pci,
Aaron Durbin76c37002012-10-30 09:03:43 -0500867};
868
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800869static const unsigned short pci_device_ids[] = {
870 0x8c3a, /* Mobile */
871 0x9c3a, /* Low Power */
872 0
873};
874
Aaron Durbin76c37002012-10-30 09:03:43 -0500875static const struct pci_driver intel_me __pci_driver = {
876 .ops = &device_ops,
877 .vendor = PCI_VENDOR_ID_INTEL,
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800878 .devices= pci_device_ids,
Aaron Durbin76c37002012-10-30 09:03:43 -0500879};
880
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200881#endif /* !__SIMPLE_DEVICE__ */
882
Aaron Durbin76c37002012-10-30 09:03:43 -0500883/******************************************************************************
884 * */
885static u32 me_to_host_words_pending(void)
886{
887 struct mei_csr me;
888 read_me_csr(&me);
889 if (!me.ready)
890 return 0;
891 return (me.buffer_write_ptr - me.buffer_read_ptr) &
892 (me.buffer_depth - 1);
893}
894
895#if 0
896/* This function is not yet being used, keep it in for the future. */
897static u32 host_to_me_words_room(void)
898{
899 struct mei_csr csr;
900
901 read_me_csr(&csr);
902 if (!csr.ready)
903 return 0;
904
905 read_host_csr(&csr);
906 return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) &
907 (csr.buffer_depth - 1);
908}
909#endif
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500910
Aaron Durbinbe985242012-12-12 12:40:33 -0600911struct mbp_payload {
912 mbp_header header;
913 u32 data[0];
914};
915
Aaron Durbin76c37002012-10-30 09:03:43 -0500916/*
917 * mbp seems to be following its own flow, let's retrieve it in a dedicated
918 * function.
919 */
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200920static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500921{
922 mbp_header mbp_hdr;
Aaron Durbin76c37002012-10-30 09:03:43 -0500923 u32 me2host_pending;
Aaron Durbin76c37002012-10-30 09:03:43 -0500924 struct mei_csr host;
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500925 struct me_hfs2 hfs2;
Aaron Durbinbe985242012-12-12 12:40:33 -0600926 struct mbp_payload *mbp;
927 int i;
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500928
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200929#ifdef __SIMPLE_DEVICE__
930 pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2);
931#else
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500932 pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
Kyösti Mälkki21d6a272019-11-05 18:50:38 +0200933#endif
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500934
935 if (!hfs2.mbp_rdy) {
936 printk(BIOS_ERR, "ME: MBP not ready\n");
937 goto mbp_failure;
938 }
Aaron Durbin76c37002012-10-30 09:03:43 -0500939
940 me2host_pending = me_to_host_words_pending();
941 if (!me2host_pending) {
942 printk(BIOS_ERR, "ME: no mbp data!\n");
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500943 goto mbp_failure;
Aaron Durbin76c37002012-10-30 09:03:43 -0500944 }
945
946 /* we know for sure that at least the header is there */
947 mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW);
948
949 if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) ||
950 (me2host_pending < mbp_hdr.mbp_size)) {
951 printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words"
952 " buffer contains %d words\n",
953 mbp_hdr.num_entries, mbp_hdr.mbp_size,
954 me2host_pending);
Aaron Durbin9aa031e2012-11-02 09:16:46 -0500955 goto mbp_failure;
Aaron Durbin76c37002012-10-30 09:03:43 -0500956 }
Aaron Durbinbe985242012-12-12 12:40:33 -0600957 mbp = malloc(mbp_hdr.mbp_size * sizeof(u32));
958 if (!mbp)
959 goto mbp_failure;
Aaron Durbin76c37002012-10-30 09:03:43 -0500960
Aaron Durbinbe985242012-12-12 12:40:33 -0600961 mbp->header = mbp_hdr;
Aaron Durbin76c37002012-10-30 09:03:43 -0500962 me2host_pending--;
Aaron Durbin76c37002012-10-30 09:03:43 -0500963
Aaron Durbinbe985242012-12-12 12:40:33 -0600964 i = 0;
965 while (i != me2host_pending) {
966 mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW);
967 i++;
Aaron Durbin76c37002012-10-30 09:03:43 -0500968 }
969
Aaron Durbinbe985242012-12-12 12:40:33 -0600970 /* Signal to the ME that the host has finished reading the MBP. */
Aaron Durbin76c37002012-10-30 09:03:43 -0500971 read_host_csr(&host);
972 host.interrupt_generate = 1;
973 write_host_csr(&host);
974
Julius Wernercd49cce2019-03-05 16:53:33 -0800975#if !CONFIG(ME_MBP_CLEAR_LATE)
Aaron Durbinbe985242012-12-12 12:40:33 -0600976 /* Wait for the mbp_cleared indicator. */
Duncan Laurie3d299c42013-07-19 08:48:05 -0700977 intel_me_mbp_clear(dev);
978#endif
Aaron Durbin76c37002012-10-30 09:03:43 -0500979
Aaron Durbinbe985242012-12-12 12:40:33 -0600980 /* Dump out the MBP contents. */
Kyösti Mälkkic86fc8e2019-11-06 06:32:27 +0200981 if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) {
982 printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
983 mbp->header.num_entries, mbp->header.mbp_size);
984 if (CONFIG(DEBUG_INTEL_ME)) {
985 for (i = 0; i < mbp->header.mbp_size - 1; i++) {
986 printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
987 }
988 }
Aaron Durbinbe985242012-12-12 12:40:33 -0600989 }
Aaron Durbinbe985242012-12-12 12:40:33 -0600990
991 #define ASSIGN_FIELD_PTR(field_,val_) \
992 { \
993 mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \
994 break; \
995 }
996 /* Setup the pointers in the me_bios_payload structure. */
997 for (i = 0; i < mbp->header.mbp_size - 1;) {
998 mbp_item_header *item = (void *)&mbp->data[i];
999
Elyes HAOUASf9de5a42018-05-03 17:21:02 +02001000 switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
Aaron Durbinbe985242012-12-12 12:40:33 -06001001 case MBP_IDENT(KERNEL, FW_VER):
1002 ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
1003
1004 case MBP_IDENT(ICC, PROFILE):
1005 ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]);
1006
1007 case MBP_IDENT(INTEL_AT, STATE):
1008 ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]);
1009
1010 case MBP_IDENT(KERNEL, FW_CAP):
1011 ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]);
1012
1013 case MBP_IDENT(KERNEL, ROM_BIST):
1014 ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]);
1015
1016 case MBP_IDENT(KERNEL, PLAT_KEY):
1017 ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]);
1018
1019 case MBP_IDENT(KERNEL, FW_TYPE):
1020 ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]);
1021
1022 case MBP_IDENT(KERNEL, MFS_FAILURE):
1023 ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]);
1024
Duncan Laurie144f7b22013-05-01 11:27:58 -07001025 case MBP_IDENT(KERNEL, PLAT_TIME):
1026 ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]);
1027
1028 case MBP_IDENT(NFC, SUPPORT_DATA):
1029 ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]);
1030
Aaron Durbinbe985242012-12-12 12:40:33 -06001031 default:
Duncan Laurie0b3cd362013-08-08 15:40:01 -07001032 printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ "
1033 "dw offset 0x%x\n", mbp->data[i], i);
Aaron Durbinbe985242012-12-12 12:40:33 -06001034 break;
1035 }
1036 i += item->length;
1037 }
1038 #undef ASSIGN_FIELD_PTR
1039
Aaron Durbin76c37002012-10-30 09:03:43 -05001040 return 0;
Aaron Durbin9aa031e2012-11-02 09:16:46 -05001041
1042mbp_failure:
Kyösti Mälkki21d6a272019-11-05 18:50:38 +02001043#ifdef __SIMPLE_DEVICE__
1044 intel_me_mbp_give_up(PCI_BDF(dev));
1045#else
Aaron Durbin9aa031e2012-11-02 09:16:46 -05001046 intel_me_mbp_give_up(dev);
Kyösti Mälkki21d6a272019-11-05 18:50:38 +02001047#endif
Aaron Durbin9aa031e2012-11-02 09:16:46 -05001048 return -1;
Aaron Durbin76c37002012-10-30 09:03:43 -05001049}