Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | |
| 4 | /* |
| 5 | * This is a ramstage driver for the Intel Management Engine found in the |
| 6 | * 6-series chipset. It handles the required boot-time messages over the |
| 7 | * MMIO-based Management Engine Interface to tell the ME that the BIOS is |
| 8 | * finished with POST. Additional messages are defined for debug but are |
| 9 | * not used unless the console loglevel is high enough. |
| 10 | */ |
| 11 | |
| 12 | #include <arch/acpi.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 13 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 14 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | #include <console/console.h> |
Stefan Reinauer | 24d1d4b | 2013-03-21 11:51:41 -0700 | [diff] [blame] | 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | #include <device/pci_ids.h> |
| 19 | #include <device/pci_def.h> |
| 20 | #include <string.h> |
| 21 | #include <delay.h> |
| 22 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 23 | #include <halt.h> |
Elyes HAOUAS | 400f9ca | 2019-06-23 07:01:22 +0200 | [diff] [blame] | 24 | #include <stdlib.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 26 | #include "chip.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | #include "me.h" |
| 28 | #include "pch.h" |
| 29 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 30 | #if CONFIG(CHROMEOS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | #include <vendorcode/google/chromeos/chromeos.h> |
| 32 | #include <vendorcode/google/chromeos/gnvs.h> |
| 33 | #endif |
| 34 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | /* Path that the BIOS should take based on ME state */ |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 36 | static const char *me_bios_path_values[] __unused = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | [ME_NORMAL_BIOS_PATH] = "Normal", |
| 38 | [ME_S3WAKE_BIOS_PATH] = "S3 Wake", |
| 39 | [ME_ERROR_BIOS_PATH] = "Error", |
| 40 | [ME_RECOVERY_BIOS_PATH] = "Recovery", |
| 41 | [ME_DISABLE_BIOS_PATH] = "Disable", |
| 42 | [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", |
| 43 | }; |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 44 | static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | |
| 46 | /* MMIO base address for MEI interface */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | static u32 *mei_base_address; |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 48 | #ifdef __SIMPLE_DEVICE__ |
| 49 | void intel_me_mbp_clear(pci_devfn_t dev); |
| 50 | #else |
| 51 | void intel_me_mbp_clear(struct device *dev); |
| 52 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | static void mei_dump(void *ptr, int dword, int offset, const char *type) |
| 55 | { |
| 56 | struct mei_csr *csr; |
| 57 | |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 58 | if (!CONFIG(DEBUG_INTEL_ME)) |
| 59 | return; |
| 60 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 61 | printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); |
| 62 | |
| 63 | switch (offset) { |
| 64 | case MEI_H_CSR: |
| 65 | case MEI_ME_CSR_HA: |
| 66 | csr = ptr; |
| 67 | if (!csr) { |
| 68 | printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); |
| 69 | break; |
| 70 | } |
| 71 | printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " |
| 72 | "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, |
| 73 | csr->buffer_read_ptr, csr->buffer_write_ptr, |
| 74 | csr->ready, csr->reset, csr->interrupt_generate, |
| 75 | csr->interrupt_status, csr->interrupt_enable); |
| 76 | break; |
| 77 | case MEI_ME_CB_RW: |
| 78 | case MEI_H_CB_WW: |
| 79 | printk(BIOS_SPEW, "CB: 0x%08x\n", dword); |
| 80 | break; |
| 81 | default: |
| 82 | printk(BIOS_SPEW, "0x%08x\n", offset); |
| 83 | break; |
| 84 | } |
| 85 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * ME/MEI access helpers using memcpy to avoid aliasing. |
| 89 | */ |
| 90 | |
| 91 | static inline void mei_read_dword_ptr(void *ptr, int offset) |
| 92 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 93 | u32 dword = read32(mei_base_address + (offset/sizeof(u32))); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | memcpy(ptr, &dword, sizeof(dword)); |
| 95 | mei_dump(ptr, dword, offset, "READ"); |
| 96 | } |
| 97 | |
| 98 | static inline void mei_write_dword_ptr(void *ptr, int offset) |
| 99 | { |
| 100 | u32 dword = 0; |
| 101 | memcpy(&dword, ptr, sizeof(dword)); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 102 | write32(mei_base_address + (offset/sizeof(u32)), dword); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | mei_dump(ptr, dword, offset, "WRITE"); |
| 104 | } |
| 105 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 106 | #ifdef __SIMPLE_DEVICE__ |
| 107 | static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset) |
| 108 | #else |
| 109 | static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) |
| 110 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | { |
| 112 | u32 dword = pci_read_config32(dev, offset); |
| 113 | memcpy(ptr, &dword, sizeof(dword)); |
| 114 | mei_dump(ptr, dword, offset, "PCI READ"); |
| 115 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | |
| 117 | static inline void read_host_csr(struct mei_csr *csr) |
| 118 | { |
| 119 | mei_read_dword_ptr(csr, MEI_H_CSR); |
| 120 | } |
| 121 | |
| 122 | static inline void write_host_csr(struct mei_csr *csr) |
| 123 | { |
| 124 | mei_write_dword_ptr(csr, MEI_H_CSR); |
| 125 | } |
| 126 | |
| 127 | static inline void read_me_csr(struct mei_csr *csr) |
| 128 | { |
| 129 | mei_read_dword_ptr(csr, MEI_ME_CSR_HA); |
| 130 | } |
| 131 | |
| 132 | static inline void write_cb(u32 dword) |
| 133 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 134 | write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); |
| 136 | } |
| 137 | |
| 138 | static inline u32 read_cb(void) |
| 139 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 140 | u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); |
| 142 | return dword; |
| 143 | } |
| 144 | |
| 145 | /* Wait for ME ready bit to be asserted */ |
| 146 | static int mei_wait_for_me_ready(void) |
| 147 | { |
| 148 | struct mei_csr me; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 149 | unsigned int try = ME_RETRY; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 150 | |
| 151 | while (try--) { |
| 152 | read_me_csr(&me); |
| 153 | if (me.ready) |
| 154 | return 0; |
| 155 | udelay(ME_DELAY); |
| 156 | } |
| 157 | |
| 158 | printk(BIOS_ERR, "ME: failed to become ready\n"); |
| 159 | return -1; |
| 160 | } |
| 161 | |
| 162 | static void mei_reset(void) |
| 163 | { |
| 164 | struct mei_csr host; |
| 165 | |
| 166 | if (mei_wait_for_me_ready() < 0) |
| 167 | return; |
| 168 | |
| 169 | /* Reset host and ME circular buffers for next message */ |
| 170 | read_host_csr(&host); |
| 171 | host.reset = 1; |
| 172 | host.interrupt_generate = 1; |
| 173 | write_host_csr(&host); |
| 174 | |
| 175 | if (mei_wait_for_me_ready() < 0) |
| 176 | return; |
| 177 | |
| 178 | /* Re-init and indicate host is ready */ |
| 179 | read_host_csr(&host); |
| 180 | host.interrupt_generate = 1; |
| 181 | host.ready = 1; |
| 182 | host.reset = 0; |
| 183 | write_host_csr(&host); |
| 184 | } |
| 185 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 186 | static int mei_send_packet(struct mei_header *mei, void *req_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 187 | { |
| 188 | struct mei_csr host; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 189 | unsigned int ndata, n; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 190 | u32 *data; |
| 191 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 192 | /* Number of dwords to write */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 193 | ndata = mei->length >> 2; |
| 194 | |
| 195 | /* Pad non-dword aligned request message length */ |
| 196 | if (mei->length & 3) |
| 197 | ndata++; |
| 198 | if (!ndata) { |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 199 | printk(BIOS_DEBUG, "ME: request has no data\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 200 | return -1; |
| 201 | } |
| 202 | ndata++; /* Add MEI header */ |
| 203 | |
| 204 | /* |
| 205 | * Make sure there is still room left in the circular buffer. |
| 206 | * Reset the buffer pointers if the requested message will not fit. |
| 207 | */ |
| 208 | read_host_csr(&host); |
| 209 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 210 | printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); |
| 211 | mei_reset(); |
| 212 | read_host_csr(&host); |
| 213 | } |
| 214 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 215 | /* Ensure the requested length will fit in the circular buffer. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 216 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 217 | printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", |
| 218 | ndata + 2, host.buffer_depth); |
| 219 | return -1; |
| 220 | } |
| 221 | |
| 222 | /* Write MEI header */ |
| 223 | mei_write_dword_ptr(mei, MEI_H_CB_WW); |
| 224 | ndata--; |
| 225 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 226 | /* Write message data */ |
| 227 | data = req_data; |
| 228 | for (n = 0; n < ndata; ++n) |
| 229 | write_cb(*data++); |
| 230 | |
| 231 | /* Generate interrupt to the ME */ |
| 232 | read_host_csr(&host); |
| 233 | host.interrupt_generate = 1; |
| 234 | write_host_csr(&host); |
| 235 | |
| 236 | /* Make sure ME is ready after sending request data */ |
| 237 | return mei_wait_for_me_ready(); |
| 238 | } |
| 239 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 240 | static int mei_send_data(u8 me_address, u8 host_address, |
| 241 | void *req_data, int req_bytes) |
| 242 | { |
| 243 | struct mei_header header = { |
| 244 | .client_address = me_address, |
| 245 | .host_address = host_address, |
| 246 | }; |
| 247 | struct mei_csr host; |
| 248 | int current = 0; |
| 249 | u8 *req_ptr = req_data; |
| 250 | |
| 251 | while (!header.is_complete) { |
| 252 | int remain = req_bytes - current; |
| 253 | int buf_len; |
| 254 | |
| 255 | read_host_csr(&host); |
| 256 | buf_len = host.buffer_depth - host.buffer_write_ptr; |
| 257 | |
| 258 | if (buf_len > remain) { |
| 259 | /* Send all remaining data as final message */ |
| 260 | header.length = req_bytes - current; |
| 261 | header.is_complete = 1; |
| 262 | } else { |
| 263 | /* Send as much data as the buffer can hold */ |
| 264 | header.length = buf_len; |
| 265 | } |
| 266 | |
| 267 | mei_send_packet(&header, req_ptr); |
| 268 | |
| 269 | req_ptr += header.length; |
| 270 | current += header.length; |
| 271 | } |
| 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
| 276 | static int mei_send_header(u8 me_address, u8 host_address, |
| 277 | void *header, int header_len, int complete) |
| 278 | { |
| 279 | struct mei_header mei = { |
| 280 | .client_address = me_address, |
| 281 | .host_address = host_address, |
| 282 | .length = header_len, |
| 283 | .is_complete = complete, |
| 284 | }; |
| 285 | return mei_send_packet(&mei, header); |
| 286 | } |
| 287 | |
| 288 | static int mei_recv_msg(void *header, int header_bytes, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 289 | void *rsp_data, int rsp_bytes) |
| 290 | { |
| 291 | struct mei_header mei_rsp; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 292 | struct mei_csr me, host; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 293 | unsigned int ndata, n; |
| 294 | unsigned int expected; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 295 | u32 *data; |
| 296 | |
| 297 | /* Total number of dwords to read from circular buffer */ |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 298 | expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 299 | if (rsp_bytes & 3) |
| 300 | expected++; |
| 301 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 302 | if (mei_wait_for_me_ready() < 0) |
| 303 | return -1; |
| 304 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 305 | /* |
| 306 | * The interrupt status bit does not appear to indicate that the |
| 307 | * message has actually been received. Instead we wait until the |
| 308 | * expected number of dwords are present in the circular buffer. |
| 309 | */ |
| 310 | for (n = ME_RETRY; n; --n) { |
| 311 | read_me_csr(&me); |
| 312 | if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) |
| 313 | break; |
| 314 | udelay(ME_DELAY); |
| 315 | } |
| 316 | if (!n) { |
| 317 | printk(BIOS_ERR, "ME: timeout waiting for data: expected " |
| 318 | "%u, available %u\n", expected, |
| 319 | me.buffer_write_ptr - me.buffer_read_ptr); |
| 320 | return -1; |
| 321 | } |
| 322 | |
| 323 | /* Read and verify MEI response header from the ME */ |
| 324 | mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); |
| 325 | if (!mei_rsp.is_complete) { |
| 326 | printk(BIOS_ERR, "ME: response is not complete\n"); |
| 327 | return -1; |
| 328 | } |
| 329 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 330 | /* Handle non-dword responses and expect at least the header */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 331 | ndata = mei_rsp.length >> 2; |
| 332 | if (mei_rsp.length & 3) |
| 333 | ndata++; |
| 334 | if (ndata != (expected - 1)) { |
| 335 | printk(BIOS_ERR, "ME: response is missing data %d != %d\n", |
| 336 | ndata, (expected - 1)); |
| 337 | return -1; |
| 338 | } |
| 339 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 340 | /* Read response header from the ME */ |
| 341 | data = header; |
| 342 | for (n = 0; n < (header_bytes >> 2); ++n) |
| 343 | *data++ = read_cb(); |
| 344 | ndata -= header_bytes >> 2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 345 | |
| 346 | /* Make sure caller passed a buffer with enough space */ |
| 347 | if (ndata != (rsp_bytes >> 2)) { |
| 348 | printk(BIOS_ERR, "ME: not enough room in response buffer: " |
| 349 | "%u != %u\n", ndata, rsp_bytes >> 2); |
| 350 | return -1; |
| 351 | } |
| 352 | |
| 353 | /* Read response data from the circular buffer */ |
| 354 | data = rsp_data; |
| 355 | for (n = 0; n < ndata; ++n) |
| 356 | *data++ = read_cb(); |
| 357 | |
| 358 | /* Tell the ME that we have consumed the response */ |
| 359 | read_host_csr(&host); |
| 360 | host.interrupt_status = 1; |
| 361 | host.interrupt_generate = 1; |
| 362 | write_host_csr(&host); |
| 363 | |
| 364 | return mei_wait_for_me_ready(); |
| 365 | } |
| 366 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 367 | static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, |
| 368 | void *req_data, int req_bytes, |
| 369 | void *rsp_data, int rsp_bytes) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 370 | { |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 371 | struct mkhi_header mkhi_rsp; |
| 372 | |
| 373 | /* Send header */ |
| 374 | if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 375 | mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 376 | return -1; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 377 | |
| 378 | /* Send data if available */ |
| 379 | if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 380 | req_data, req_bytes) < 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 381 | return -1; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 382 | |
| 383 | /* Return now if no response expected */ |
| 384 | if (!rsp_bytes) |
| 385 | return 0; |
| 386 | |
| 387 | /* Read header and data */ |
| 388 | if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), |
| 389 | rsp_data, rsp_bytes) < 0) |
| 390 | return -1; |
| 391 | |
| 392 | if (!mkhi_rsp.is_response || |
| 393 | mkhi->group_id != mkhi_rsp.group_id || |
| 394 | mkhi->command != mkhi_rsp.command) { |
| 395 | printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," |
| 396 | "command %u ?= %u, is_response %u\n", mkhi->group_id, |
| 397 | mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, |
| 398 | mkhi_rsp.is_response); |
| 399 | return -1; |
| 400 | } |
| 401 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 402 | return 0; |
| 403 | } |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 404 | |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 405 | /* |
| 406 | * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read |
| 407 | * state machine on the BIOS end doesn't match the ME's state machine. |
| 408 | */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 409 | #ifdef __SIMPLE_DEVICE__ |
| 410 | static void intel_me_mbp_give_up(pci_devfn_t dev) |
| 411 | #else |
| 412 | static void intel_me_mbp_give_up(struct device *dev) |
| 413 | #endif |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 414 | { |
| 415 | struct mei_csr csr; |
| 416 | |
| 417 | pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); |
| 418 | |
| 419 | read_host_csr(&csr); |
| 420 | csr.reset = 1; |
| 421 | csr.interrupt_generate = 1; |
| 422 | write_host_csr(&csr); |
| 423 | } |
| 424 | |
| 425 | /* |
| 426 | * mbp clear routine. This will wait for the ME to indicate that |
| 427 | * the MBP has been read and cleared. |
| 428 | */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 429 | #ifdef __SIMPLE_DEVICE__ |
| 430 | void intel_me_mbp_clear(pci_devfn_t dev) |
| 431 | #else |
| 432 | void intel_me_mbp_clear(struct device *dev) |
| 433 | #endif |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 434 | { |
| 435 | int count; |
| 436 | struct me_hfs2 hfs2; |
| 437 | |
| 438 | /* Wait for the mbp_cleared indicator */ |
| 439 | for (count = ME_RETRY; count > 0; --count) { |
| 440 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 441 | if (hfs2.mbp_cleared) |
| 442 | break; |
| 443 | udelay(ME_DELAY); |
| 444 | } |
| 445 | |
| 446 | if (count == 0) { |
| 447 | printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); |
| 448 | intel_me_mbp_give_up(dev); |
| 449 | } else { |
| 450 | printk(BIOS_INFO, "ME: MBP cleared\n"); |
| 451 | } |
| 452 | } |
| 453 | |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 454 | static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 455 | { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 456 | if (!vers_name) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 457 | printk(BIOS_ERR, "ME: mbp missing version report\n"); |
| 458 | return; |
| 459 | } |
| 460 | |
| 461 | printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", |
| 462 | vers_name->major_version, vers_name->minor_version, |
| 463 | vers_name->hotfix_version, vers_name->build_version); |
| 464 | } |
| 465 | |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 466 | static inline void print_cap(const char *name, int state) |
| 467 | { |
| 468 | printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", |
| 469 | name, state ? " en" : "dis"); |
| 470 | } |
| 471 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 472 | /* Get ME Firmware Capabilities */ |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 473 | static int mkhi_get_fwcaps(mbp_mefwcaps *cap) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 474 | { |
| 475 | u32 rule_id = 0; |
| 476 | struct me_fwcaps cap_msg; |
| 477 | struct mkhi_header mkhi = { |
| 478 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 479 | .command = MKHI_FWCAPS_GET_RULE, |
| 480 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 481 | |
| 482 | /* Send request and wait for response */ |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 483 | if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), |
| 484 | &cap_msg, sizeof(cap_msg)) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 485 | printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); |
| 486 | return -1; |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 487 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 488 | *cap = cap_msg.caps_sku; |
| 489 | return 0; |
| 490 | } |
| 491 | |
| 492 | /* Get ME Firmware Capabilities */ |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 493 | static void __unused me_print_fwcaps(mbp_mefwcaps *cap) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 494 | { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 495 | mbp_mefwcaps local_caps; |
| 496 | if (!cap) { |
| 497 | cap = &local_caps; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 498 | printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); |
| 499 | if (mkhi_get_fwcaps(cap)) |
| 500 | return; |
| 501 | } |
| 502 | |
| 503 | print_cap("Full Network manageability", cap->full_net); |
| 504 | print_cap("Regular Network manageability", cap->std_net); |
| 505 | print_cap("Manageability", cap->manageability); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 506 | print_cap("IntelR Anti-Theft (AT)", cap->intel_at); |
| 507 | print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); |
| 508 | print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); |
| 509 | print_cap("ICC Over Clocking", cap->icc_over_clocking); |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 510 | print_cap("Protected Audio Video Path (PAVP)", cap->pavp); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 511 | print_cap("IPV6", cap->ipv6); |
| 512 | print_cap("KVM Remote Control (KVM)", cap->kvm); |
| 513 | print_cap("Outbreak Containment Heuristic (OCH)", cap->och); |
| 514 | print_cap("Virtual LAN (VLAN)", cap->vlan); |
| 515 | print_cap("TLS", cap->tls); |
| 516 | print_cap("Wireless LAN (WLAN)", cap->wlan); |
| 517 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 518 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 519 | #if CONFIG(CHROMEOS) && 0 /* DISABLED */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 520 | /* Tell ME to issue a global reset */ |
| 521 | static int mkhi_global_reset(void) |
| 522 | { |
| 523 | struct me_global_reset reset = { |
| 524 | .request_origin = GLOBAL_RESET_BIOS_POST, |
| 525 | .reset_type = CBM_RR_GLOBAL_RESET, |
| 526 | }; |
| 527 | struct mkhi_header mkhi = { |
| 528 | .group_id = MKHI_GROUP_ID_CBM, |
| 529 | .command = MKHI_GLOBAL_RESET, |
| 530 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 531 | |
| 532 | /* Send request and wait for response */ |
| 533 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 534 | if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 535 | /* No response means reset will happen shortly... */ |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 536 | halt(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | /* If the ME responded it rejected the reset request */ |
| 540 | printk(BIOS_ERR, "ME: Global Reset failed\n"); |
| 541 | return -1; |
| 542 | } |
| 543 | #endif |
| 544 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 545 | /* Send END OF POST message to the ME */ |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 546 | static int __unused mkhi_end_of_post(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 547 | { |
| 548 | struct mkhi_header mkhi = { |
| 549 | .group_id = MKHI_GROUP_ID_GEN, |
| 550 | .command = MKHI_END_OF_POST, |
| 551 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 552 | u32 eop_ack; |
| 553 | |
| 554 | /* Send request and wait for response */ |
| 555 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 556 | if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 557 | printk(BIOS_ERR, "ME: END OF POST message failed\n"); |
| 558 | return -1; |
| 559 | } |
| 560 | |
| 561 | printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); |
| 562 | return 0; |
| 563 | } |
| 564 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 565 | #ifdef __SIMPLE_DEVICE__ |
| 566 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 567 | void intel_me_finalize_smm(void) |
| 568 | { |
| 569 | struct me_hfs hfs; |
| 570 | u32 reg32; |
| 571 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 572 | mei_base_address = (u32 *) |
| 573 | (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 574 | |
| 575 | /* S3 path will have hidden this device already */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 576 | if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 577 | return; |
| 578 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 579 | #if CONFIG(ME_MBP_CLEAR_LATE) |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 580 | /* Wait for ME MBP Cleared indicator */ |
| 581 | intel_me_mbp_clear(PCH_ME_DEV); |
| 582 | #endif |
| 583 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 584 | /* Make sure ME is in a mode that expects EOP */ |
| 585 | reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); |
| 586 | memcpy(&hfs, ®32, sizeof(u32)); |
| 587 | |
| 588 | /* Abort and leave device alone if not normal mode */ |
| 589 | if (hfs.fpt_bad || |
| 590 | hfs.working_state != ME_HFS_CWS_NORMAL || |
| 591 | hfs.operation_mode != ME_HFS_MODE_NORMAL) |
| 592 | return; |
| 593 | |
| 594 | /* Try to send EOP command so ME stops accepting other commands */ |
| 595 | mkhi_end_of_post(); |
| 596 | |
| 597 | /* Make sure IO is disabled */ |
| 598 | reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); |
| 599 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 600 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 601 | pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); |
| 602 | |
| 603 | /* Hide the PCI device */ |
| 604 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 605 | } |
| 606 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 607 | #else /* !__SIMPLE_DEVICE__ */ |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 608 | |
Edward O'Callaghan | 97ccefd | 2015-01-07 15:53:00 +1100 | [diff] [blame] | 609 | static inline int mei_sendrecv_icc(struct icc_header *icc, |
| 610 | void *req_data, int req_bytes, |
| 611 | void *rsp_data, int rsp_bytes) |
| 612 | { |
| 613 | struct icc_header icc_rsp; |
| 614 | |
| 615 | /* Send header */ |
| 616 | if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 617 | icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) |
| 618 | return -1; |
| 619 | |
| 620 | /* Send data if available */ |
| 621 | if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 622 | req_data, req_bytes) < 0) |
| 623 | return -1; |
| 624 | |
| 625 | /* Read header and data, if needed */ |
| 626 | if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), |
| 627 | rsp_data, rsp_bytes) < 0) |
| 628 | return -1; |
| 629 | |
| 630 | return 0; |
| 631 | } |
| 632 | |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 633 | static int me_icc_set_clock_enables(u32 mask) |
| 634 | { |
| 635 | struct icc_clock_enables_msg clk = { |
| 636 | .clock_enables = 0, /* Turn off specified clocks */ |
| 637 | .clock_mask = mask, |
| 638 | .no_response = 1, /* Do not expect response */ |
| 639 | }; |
| 640 | struct icc_header icc = { |
| 641 | .api_version = ICC_API_VERSION_LYNXPOINT, |
| 642 | .icc_command = ICC_SET_CLOCK_ENABLES, |
| 643 | .length = sizeof(clk), |
| 644 | }; |
| 645 | |
| 646 | /* Send request and wait for response */ |
| 647 | if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { |
| 648 | printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); |
| 649 | return -1; |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 650 | } |
| 651 | |
Elyes HAOUAS | 54f9424 | 2018-10-25 10:57:39 +0200 | [diff] [blame] | 652 | printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 653 | return 0; |
| 654 | } |
| 655 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 656 | /* Determine the path that we should take based on ME status */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 657 | static me_bios_path intel_me_path(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 658 | { |
| 659 | me_bios_path path = ME_DISABLE_BIOS_PATH; |
| 660 | struct me_hfs hfs; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 661 | struct me_hfs2 hfs2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 662 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 663 | pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 664 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 665 | |
| 666 | /* Check and dump status */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 667 | intel_me_status(&hfs, &hfs2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 668 | |
| 669 | /* Check Current Working State */ |
| 670 | switch (hfs.working_state) { |
| 671 | case ME_HFS_CWS_NORMAL: |
| 672 | path = ME_NORMAL_BIOS_PATH; |
| 673 | break; |
| 674 | case ME_HFS_CWS_REC: |
| 675 | path = ME_RECOVERY_BIOS_PATH; |
| 676 | break; |
| 677 | default: |
| 678 | path = ME_DISABLE_BIOS_PATH; |
| 679 | break; |
| 680 | } |
| 681 | |
| 682 | /* Check Current Operation Mode */ |
| 683 | switch (hfs.operation_mode) { |
| 684 | case ME_HFS_MODE_NORMAL: |
| 685 | break; |
| 686 | case ME_HFS_MODE_DEBUG: |
| 687 | case ME_HFS_MODE_DIS: |
| 688 | case ME_HFS_MODE_OVER_JMPR: |
| 689 | case ME_HFS_MODE_OVER_MEI: |
| 690 | default: |
| 691 | path = ME_DISABLE_BIOS_PATH; |
| 692 | break; |
| 693 | } |
| 694 | |
| 695 | /* Check for any error code and valid firmware and MBP */ |
| 696 | if (hfs.error_code || hfs.fpt_bad) |
| 697 | path = ME_ERROR_BIOS_PATH; |
| 698 | |
| 699 | /* Check if the MBP is ready */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 700 | if (!hfs2.mbp_rdy) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 701 | printk(BIOS_CRIT, "%s: mbp is not ready!\n", |
| 702 | __FUNCTION__); |
| 703 | path = ME_ERROR_BIOS_PATH; |
| 704 | } |
| 705 | |
Kyösti Mälkki | be5317f | 2019-11-06 12:07:21 +0200 | [diff] [blame] | 706 | if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 707 | struct elog_event_data_me_extended data = { |
| 708 | .current_working_state = hfs.working_state, |
| 709 | .operation_state = hfs.operation_state, |
| 710 | .operation_mode = hfs.operation_mode, |
| 711 | .error_code = hfs.error_code, |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 712 | .progress_code = hfs2.progress_code, |
| 713 | .current_pmevent = hfs2.current_pmevent, |
| 714 | .current_state = hfs2.current_state, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 715 | }; |
| 716 | elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); |
| 717 | elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, |
| 718 | &data, sizeof(data)); |
| 719 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 720 | |
| 721 | return path; |
| 722 | } |
| 723 | |
| 724 | /* Prepare ME for MEI messages */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 725 | static int intel_mei_setup(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 726 | { |
| 727 | struct resource *res; |
| 728 | struct mei_csr host; |
| 729 | u32 reg32; |
| 730 | |
| 731 | /* Find the MMIO base for the ME interface */ |
| 732 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 733 | if (!res || res->base == 0 || res->size == 0) { |
| 734 | printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); |
| 735 | return -1; |
| 736 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 737 | mei_base_address = (u32 *)(uintptr_t)res->base; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 738 | |
| 739 | /* Ensure Memory and Bus Master bits are set */ |
| 740 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 741 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 742 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 743 | |
| 744 | /* Clean up status for next message */ |
| 745 | read_host_csr(&host); |
| 746 | host.interrupt_generate = 1; |
| 747 | host.ready = 1; |
| 748 | host.reset = 0; |
| 749 | write_host_csr(&host); |
| 750 | |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | /* Read the Extend register hash of ME firmware */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 755 | static int intel_me_extend_valid(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 756 | { |
| 757 | struct me_heres status; |
| 758 | u32 extend[8] = {0}; |
| 759 | int i, count = 0; |
| 760 | |
| 761 | pci_read_dword_ptr(dev, &status, PCI_ME_HERES); |
| 762 | if (!status.extend_feature_present) { |
| 763 | printk(BIOS_ERR, "ME: Extend Feature not present\n"); |
| 764 | return -1; |
| 765 | } |
| 766 | |
| 767 | if (!status.extend_reg_valid) { |
| 768 | printk(BIOS_ERR, "ME: Extend Register not valid\n"); |
| 769 | return -1; |
| 770 | } |
| 771 | |
| 772 | switch (status.extend_reg_algorithm) { |
| 773 | case PCI_ME_EXT_SHA1: |
| 774 | count = 5; |
| 775 | printk(BIOS_DEBUG, "ME: Extend SHA-1: "); |
| 776 | break; |
| 777 | case PCI_ME_EXT_SHA256: |
| 778 | count = 8; |
| 779 | printk(BIOS_DEBUG, "ME: Extend SHA-256: "); |
| 780 | break; |
| 781 | default: |
| 782 | printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", |
| 783 | status.extend_reg_algorithm); |
| 784 | return -1; |
| 785 | } |
| 786 | |
| 787 | for (i = 0; i < count; ++i) { |
| 788 | extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); |
| 789 | printk(BIOS_DEBUG, "%08x", extend[i]); |
| 790 | } |
| 791 | printk(BIOS_DEBUG, "\n"); |
| 792 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 793 | #if CONFIG(CHROMEOS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 794 | /* Save hash in NVS for the OS to verify */ |
| 795 | chromeos_set_me_hash(extend, count); |
| 796 | #endif |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 801 | /* Check whether ME is present and do basic init */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 802 | static void intel_me_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 803 | { |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 804 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 805 | me_bios_path path = intel_me_path(dev); |
| 806 | me_bios_payload mbp_data; |
| 807 | |
| 808 | /* Do initial setup and determine the BIOS path */ |
| 809 | printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); |
| 810 | |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 811 | if (path == ME_NORMAL_BIOS_PATH) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 812 | /* Validate the extend register */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 813 | intel_me_extend_valid(dev); |
| 814 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 815 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 816 | memset(&mbp_data, 0, sizeof(mbp_data)); |
| 817 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 818 | /* |
| 819 | * According to the ME9 BWG, BIOS is required to fetch MBP data in |
| 820 | * all boot flows except S3 Resume. |
| 821 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 822 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 823 | /* Prepare MEI MMIO interface */ |
| 824 | if (intel_mei_setup(dev) < 0) |
| 825 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 826 | |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 827 | if (intel_me_read_mbp(&mbp_data, dev)) |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 828 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 829 | |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 830 | if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { |
| 831 | me_print_fw_version(mbp_data.fw_version_name); |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 832 | |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 833 | if (CONFIG(DEBUG_INTEL_ME)) |
| 834 | me_print_fwcaps(mbp_data.fw_capabilities); |
| 835 | |
| 836 | if (mbp_data.plat_time) { |
| 837 | printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", |
| 838 | mbp_data.plat_time->wake_event_mrst_time_ms); |
| 839 | printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", |
| 840 | mbp_data.plat_time->mrst_pltrst_time_ms); |
| 841 | printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", |
| 842 | mbp_data.plat_time->pltrst_cpurst_time_ms); |
| 843 | } |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 844 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 845 | |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 846 | /* Set clock enables according to devicetree */ |
| 847 | if (config && config->icc_clock_disable) |
| 848 | me_icc_set_clock_enables(config->icc_clock_disable); |
| 849 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 850 | /* |
| 851 | * Leave the ME unlocked. It will be locked via SMI command later. |
| 852 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 853 | } |
| 854 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 855 | static struct pci_operations pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 856 | .set_subsystem = pci_dev_set_subsystem, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 857 | }; |
| 858 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 859 | static void intel_me_enable(struct device *dev) |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 860 | { |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 861 | /* Avoid talking to the device in S3 path */ |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 862 | if (acpi_is_wakeup_s3()) { |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 863 | dev->enabled = 0; |
| 864 | pch_disable_devfn(dev); |
| 865 | } |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 866 | } |
| 867 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 868 | static struct device_operations device_ops = { |
| 869 | .read_resources = pci_dev_read_resources, |
| 870 | .set_resources = pci_dev_set_resources, |
| 871 | .enable_resources = pci_dev_enable_resources, |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 872 | .enable = intel_me_enable, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 873 | .init = intel_me_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 874 | .ops_pci = &pci_ops, |
| 875 | }; |
| 876 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 877 | static const unsigned short pci_device_ids[] = { |
| 878 | 0x8c3a, /* Mobile */ |
| 879 | 0x9c3a, /* Low Power */ |
| 880 | 0 |
| 881 | }; |
| 882 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 883 | static const struct pci_driver intel_me __pci_driver = { |
| 884 | .ops = &device_ops, |
| 885 | .vendor = PCI_VENDOR_ID_INTEL, |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 886 | .devices= pci_device_ids, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 887 | }; |
| 888 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 889 | #endif /* !__SIMPLE_DEVICE__ */ |
| 890 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 891 | /****************************************************************************** |
| 892 | * */ |
| 893 | static u32 me_to_host_words_pending(void) |
| 894 | { |
| 895 | struct mei_csr me; |
| 896 | read_me_csr(&me); |
| 897 | if (!me.ready) |
| 898 | return 0; |
| 899 | return (me.buffer_write_ptr - me.buffer_read_ptr) & |
| 900 | (me.buffer_depth - 1); |
| 901 | } |
| 902 | |
| 903 | #if 0 |
| 904 | /* This function is not yet being used, keep it in for the future. */ |
| 905 | static u32 host_to_me_words_room(void) |
| 906 | { |
| 907 | struct mei_csr csr; |
| 908 | |
| 909 | read_me_csr(&csr); |
| 910 | if (!csr.ready) |
| 911 | return 0; |
| 912 | |
| 913 | read_host_csr(&csr); |
| 914 | return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & |
| 915 | (csr.buffer_depth - 1); |
| 916 | } |
| 917 | #endif |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 918 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 919 | struct mbp_payload { |
| 920 | mbp_header header; |
| 921 | u32 data[0]; |
| 922 | }; |
| 923 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 924 | /* |
| 925 | * mbp seems to be following its own flow, let's retrieve it in a dedicated |
| 926 | * function. |
| 927 | */ |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 928 | static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 929 | { |
| 930 | mbp_header mbp_hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 931 | u32 me2host_pending; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 932 | struct mei_csr host; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 933 | struct me_hfs2 hfs2; |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 934 | struct mbp_payload *mbp; |
| 935 | int i; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 936 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 937 | #ifdef __SIMPLE_DEVICE__ |
| 938 | pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2); |
| 939 | #else |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 940 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 941 | #endif |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 942 | |
| 943 | if (!hfs2.mbp_rdy) { |
| 944 | printk(BIOS_ERR, "ME: MBP not ready\n"); |
| 945 | goto mbp_failure; |
| 946 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 947 | |
| 948 | me2host_pending = me_to_host_words_pending(); |
| 949 | if (!me2host_pending) { |
| 950 | printk(BIOS_ERR, "ME: no mbp data!\n"); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 951 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 952 | } |
| 953 | |
| 954 | /* we know for sure that at least the header is there */ |
| 955 | mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); |
| 956 | |
| 957 | if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || |
| 958 | (me2host_pending < mbp_hdr.mbp_size)) { |
| 959 | printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" |
| 960 | " buffer contains %d words\n", |
| 961 | mbp_hdr.num_entries, mbp_hdr.mbp_size, |
| 962 | me2host_pending); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 963 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 964 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 965 | mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); |
| 966 | if (!mbp) |
| 967 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 968 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 969 | mbp->header = mbp_hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 970 | me2host_pending--; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 971 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 972 | i = 0; |
| 973 | while (i != me2host_pending) { |
| 974 | mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); |
| 975 | i++; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 976 | } |
| 977 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 978 | /* Signal to the ME that the host has finished reading the MBP. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 979 | read_host_csr(&host); |
| 980 | host.interrupt_generate = 1; |
| 981 | write_host_csr(&host); |
| 982 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 983 | #if !CONFIG(ME_MBP_CLEAR_LATE) |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 984 | /* Wait for the mbp_cleared indicator. */ |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 985 | intel_me_mbp_clear(dev); |
| 986 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 987 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 988 | /* Dump out the MBP contents. */ |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 989 | if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { |
| 990 | printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", |
| 991 | mbp->header.num_entries, mbp->header.mbp_size); |
| 992 | if (CONFIG(DEBUG_INTEL_ME)) { |
| 993 | for (i = 0; i < mbp->header.mbp_size - 1; i++) { |
| 994 | printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); |
| 995 | } |
| 996 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 997 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 998 | |
| 999 | #define ASSIGN_FIELD_PTR(field_,val_) \ |
| 1000 | { \ |
| 1001 | mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ |
| 1002 | break; \ |
| 1003 | } |
| 1004 | /* Setup the pointers in the me_bios_payload structure. */ |
| 1005 | for (i = 0; i < mbp->header.mbp_size - 1;) { |
| 1006 | mbp_item_header *item = (void *)&mbp->data[i]; |
| 1007 | |
Elyes HAOUAS | f9de5a4 | 2018-05-03 17:21:02 +0200 | [diff] [blame] | 1008 | switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1009 | case MBP_IDENT(KERNEL, FW_VER): |
| 1010 | ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); |
| 1011 | |
| 1012 | case MBP_IDENT(ICC, PROFILE): |
| 1013 | ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); |
| 1014 | |
| 1015 | case MBP_IDENT(INTEL_AT, STATE): |
| 1016 | ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); |
| 1017 | |
| 1018 | case MBP_IDENT(KERNEL, FW_CAP): |
| 1019 | ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); |
| 1020 | |
| 1021 | case MBP_IDENT(KERNEL, ROM_BIST): |
| 1022 | ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); |
| 1023 | |
| 1024 | case MBP_IDENT(KERNEL, PLAT_KEY): |
| 1025 | ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); |
| 1026 | |
| 1027 | case MBP_IDENT(KERNEL, FW_TYPE): |
| 1028 | ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); |
| 1029 | |
| 1030 | case MBP_IDENT(KERNEL, MFS_FAILURE): |
| 1031 | ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); |
| 1032 | |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 1033 | case MBP_IDENT(KERNEL, PLAT_TIME): |
| 1034 | ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); |
| 1035 | |
| 1036 | case MBP_IDENT(NFC, SUPPORT_DATA): |
| 1037 | ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); |
| 1038 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1039 | default: |
Duncan Laurie | 0b3cd36 | 2013-08-08 15:40:01 -0700 | [diff] [blame] | 1040 | printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " |
| 1041 | "dw offset 0x%x\n", mbp->data[i], i); |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1042 | break; |
| 1043 | } |
| 1044 | i += item->length; |
| 1045 | } |
| 1046 | #undef ASSIGN_FIELD_PTR |
| 1047 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1048 | return 0; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 1049 | |
| 1050 | mbp_failure: |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 1051 | #ifdef __SIMPLE_DEVICE__ |
| 1052 | intel_me_mbp_give_up(PCI_BDF(dev)); |
| 1053 | #else |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 1054 | intel_me_mbp_give_up(dev); |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 1055 | #endif |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 1056 | return -1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1057 | } |