sb/intel/lynxpoint: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I27d6aaa59e12a337f80a6d3387cc9c8ae5949384
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42154
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index d182e31..73fbf02 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -541,7 +541,6 @@
{
struct me_hfs hfs;
u32 reg32;
- u16 reg16;
mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@@ -569,9 +568,8 @@
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
- reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
+ pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
+ ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);