Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <cbfs.h> |
| 4 | #include <cf9_reset.h> |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 5 | #include <option.h> |
| 6 | #include <arch/io.h> |
| 7 | #include <cpu/x86/msr.h> |
| 8 | #include <console/console.h> |
| 9 | #include <cpu/intel/model_206ax/model_206ax.h> |
| 10 | #include <southbridge/intel/common/gpio.h> |
| 11 | #include <superio/smsc/sch5545/sch5545.h> |
| 12 | #include <superio/smsc/sch5545/sch5545_emi.h> |
| 13 | |
| 14 | #include "sch5545_ec.h" |
| 15 | |
| 16 | #define GPIO_CHASSIS_ID0 1 |
| 17 | #define GPIO_CHASSIS_ID1 17 |
| 18 | #define GPIO_CHASSIS_ID2 37 |
| 19 | #define GPIO_FRONT_PANEL_CHASSIS_DET_L 70 |
| 20 | |
| 21 | enum { |
| 22 | TDP_16 = 0x10, |
| 23 | TDP_32 = 0x20, |
| 24 | TDP_COMMON = 0xff, |
| 25 | }; |
| 26 | |
| 27 | typedef struct ec_val_reg_tdp { |
| 28 | uint8_t val; |
| 29 | uint16_t reg; |
| 30 | uint8_t tdp; |
| 31 | } ec_chassis_tdp_t; |
| 32 | |
| 33 | static const struct ec_val_reg ec_hwm_init_seq[] = { |
| 34 | { 0xa0, 0x02fc }, |
| 35 | { 0x32, 0x02fd }, |
| 36 | { 0x77, 0x0005 }, |
| 37 | { 0x0f, 0x0018 }, |
| 38 | { 0x2f, 0x0019 }, |
| 39 | { 0x2f, 0x001a }, |
| 40 | { 0x33, 0x008a }, |
| 41 | { 0x33, 0x008b }, |
| 42 | { 0x33, 0x008c }, |
| 43 | { 0x10, 0x00ba }, |
| 44 | { 0xff, 0x00d1 }, |
| 45 | { 0xff, 0x00d6 }, |
| 46 | { 0xff, 0x00db }, |
| 47 | { 0x00, 0x0048 }, |
| 48 | { 0x00, 0x0049 }, |
| 49 | { 0x00, 0x007a }, |
| 50 | { 0x00, 0x007b }, |
| 51 | { 0x00, 0x007c }, |
| 52 | { 0x00, 0x0080 }, |
| 53 | { 0x00, 0x0081 }, |
| 54 | { 0x00, 0x0082 }, |
| 55 | { 0xbb, 0x0083 }, |
| 56 | { 0xb0, 0x0084 }, |
| 57 | { 0x88, 0x01a1 }, |
| 58 | { 0x80, 0x01a4 }, |
| 59 | { 0x00, 0x0088 }, |
| 60 | { 0x00, 0x0089 }, |
| 61 | { 0x02, 0x00a0 }, |
| 62 | { 0x02, 0x00a1 }, |
| 63 | { 0x02, 0x00a2 }, |
| 64 | { 0x04, 0x00a4 }, |
| 65 | { 0x04, 0x00a5 }, |
| 66 | { 0x04, 0x00a6 }, |
| 67 | { 0x00, 0x00ab }, |
| 68 | { 0x3f, 0x00ad }, |
| 69 | { 0x07, 0x00b7 }, |
| 70 | { 0x50, 0x0062 }, |
| 71 | { 0x46, 0x0063 }, |
| 72 | { 0x50, 0x0064 }, |
| 73 | { 0x46, 0x0065 }, |
| 74 | { 0x50, 0x0066 }, |
| 75 | { 0x46, 0x0067 }, |
| 76 | { 0x98, 0x0057 }, |
| 77 | { 0x98, 0x0059 }, |
| 78 | { 0x7c, 0x0061 }, |
| 79 | { 0x00, 0x01bc }, |
| 80 | { 0x00, 0x01bd }, |
| 81 | { 0x00, 0x01bb }, |
| 82 | { 0xdd, 0x0085 }, |
| 83 | { 0xdd, 0x0086 }, |
| 84 | { 0x07, 0x0087 }, |
| 85 | { 0x5e, 0x0090 }, |
| 86 | { 0x5e, 0x0091 }, |
| 87 | { 0x5d, 0x0095 }, |
| 88 | { 0x00, 0x0096 }, |
| 89 | { 0x00, 0x0097 }, |
| 90 | { 0x00, 0x009b }, |
| 91 | { 0x86, 0x00ae }, |
| 92 | { 0x86, 0x00af }, |
| 93 | { 0x67, 0x00b3 }, |
| 94 | { 0xff, 0x00c4 }, |
| 95 | { 0xff, 0x00c5 }, |
| 96 | { 0xff, 0x00c9 }, |
| 97 | { 0x01, 0x0040 }, |
| 98 | { 0x00, 0x02fc }, |
| 99 | { 0x9a, 0x02b3 }, |
| 100 | { 0x05, 0x02b4 }, |
| 101 | { 0x01, 0x02cc }, |
| 102 | { 0x4c, 0x02d0 }, |
| 103 | { 0x01, 0x02d2 }, |
| 104 | { 0x01, 0x006f }, |
| 105 | { 0x02, 0x0070 }, |
| 106 | { 0x03, 0x0071 }, |
| 107 | }; |
| 108 | |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 109 | static const ec_chassis_tdp_t ec_hwm_chassis3[] = { |
| 110 | { 0x33, 0x0005, TDP_COMMON }, |
| 111 | { 0x2f, 0x0018, TDP_COMMON }, |
| 112 | { 0x2f, 0x0019, TDP_COMMON }, |
| 113 | { 0x2f, 0x001a, TDP_COMMON }, |
| 114 | { 0x00, 0x0080, TDP_COMMON }, |
| 115 | { 0x00, 0x0081, TDP_COMMON }, |
| 116 | { 0xbb, 0x0083, TDP_COMMON }, |
| 117 | { 0x8a, 0x0085, TDP_16 }, |
| 118 | { 0x2c, 0x0086, TDP_16 }, |
| 119 | { 0x66, 0x008a, TDP_16 }, |
| 120 | { 0x5b, 0x008b, TDP_16 }, |
| 121 | { 0x65, 0x0090, TDP_COMMON }, |
| 122 | { 0x70, 0x0091, TDP_COMMON }, |
| 123 | { 0x86, 0x0092, TDP_COMMON }, |
| 124 | { 0xa4, 0x0096, TDP_COMMON }, |
| 125 | { 0xa4, 0x0097, TDP_COMMON }, |
| 126 | { 0xa4, 0x0098, TDP_COMMON }, |
| 127 | { 0xa4, 0x009b, TDP_COMMON }, |
| 128 | { 0x0e, 0x00a0, TDP_COMMON }, |
| 129 | { 0x0e, 0x00a1, TDP_COMMON }, |
| 130 | { 0x7c, 0x00ae, TDP_COMMON }, |
| 131 | { 0x86, 0x00af, TDP_COMMON }, |
| 132 | { 0x95, 0x00b0, TDP_COMMON }, |
| 133 | { 0x9a, 0x00b3, TDP_COMMON }, |
| 134 | { 0x08, 0x00b6, TDP_COMMON }, |
| 135 | { 0x08, 0x00b7, TDP_COMMON }, |
| 136 | { 0x64, 0x00ea, TDP_COMMON }, |
| 137 | { 0xff, 0x00ef, TDP_COMMON }, |
| 138 | { 0x15, 0x00f8, TDP_COMMON }, |
| 139 | { 0x00, 0x00f9, TDP_COMMON }, |
| 140 | { 0x30, 0x00f0, TDP_COMMON }, |
| 141 | { 0x01, 0x00fd, TDP_COMMON }, |
| 142 | { 0x88, 0x01a1, TDP_COMMON }, |
| 143 | { 0x08, 0x01a2, TDP_COMMON }, |
| 144 | { 0x08, 0x01b1, TDP_COMMON }, |
| 145 | { 0x94, 0x01be, TDP_COMMON }, |
| 146 | { 0x94, 0x0280, TDP_16 }, |
| 147 | { 0x11, 0x0281, TDP_16 }, |
| 148 | { 0x03, 0x0282, TDP_COMMON }, |
| 149 | { 0x0a, 0x0283, TDP_COMMON }, |
| 150 | { 0x80, 0x0284, TDP_COMMON }, |
| 151 | { 0x03, 0x0285, TDP_COMMON }, |
| 152 | { 0x68, 0x0288, TDP_16 }, |
| 153 | { 0x10, 0x0289, TDP_16 }, |
| 154 | { 0x03, 0x028a, TDP_COMMON }, |
| 155 | { 0x0a, 0x028b, TDP_COMMON }, |
| 156 | { 0x80, 0x028c, TDP_COMMON }, |
| 157 | { 0x03, 0x028d, TDP_COMMON }, |
| 158 | }; |
| 159 | |
| 160 | static const ec_chassis_tdp_t ec_hwm_chassis4[] = { |
| 161 | { 0x33, 0x0005, TDP_COMMON }, |
| 162 | { 0x2f, 0x0018, TDP_COMMON }, |
| 163 | { 0x2f, 0x0019, TDP_COMMON }, |
| 164 | { 0x2f, 0x001a, TDP_COMMON }, |
| 165 | { 0x00, 0x0080, TDP_COMMON }, |
| 166 | { 0x00, 0x0081, TDP_COMMON }, |
| 167 | { 0xbb, 0x0083, TDP_COMMON }, |
| 168 | { 0x99, 0x0085, TDP_32 }, |
| 169 | { 0x98, 0x0085, TDP_16 }, |
| 170 | { 0xbc, 0x0086, TDP_32 }, |
| 171 | { 0x1c, 0x0086, TDP_16 }, |
| 172 | { 0x39, 0x008a, TDP_32 }, |
| 173 | { 0x3d, 0x008a, TDP_16 }, |
| 174 | { 0x40, 0x008b, TDP_32 }, |
| 175 | { 0x43, 0x008b, TDP_16 }, |
| 176 | { 0x68, 0x0090, TDP_COMMON }, |
| 177 | { 0x5e, 0x0091, TDP_COMMON }, |
| 178 | { 0x86, 0x0092, TDP_COMMON }, |
| 179 | { 0xa4, 0x0096, TDP_COMMON }, |
| 180 | { 0xa4, 0x0097, TDP_COMMON }, |
| 181 | { 0xa4, 0x0098, TDP_COMMON }, |
| 182 | { 0xa4, 0x009b, TDP_COMMON }, |
| 183 | { 0x0c, 0x00a0, TDP_COMMON }, |
| 184 | { 0x0c, 0x00a1, TDP_COMMON }, |
| 185 | { 0x72, 0x00ae, TDP_COMMON }, |
| 186 | { 0x7c, 0x00af, TDP_COMMON }, |
| 187 | { 0x9a, 0x00b0, TDP_COMMON }, |
| 188 | { 0x7c, 0x00b3, TDP_COMMON }, |
| 189 | { 0x08, 0x00b6, TDP_COMMON }, |
| 190 | { 0x08, 0x00b7, TDP_COMMON }, |
| 191 | { 0x64, 0x00ea, TDP_COMMON }, |
| 192 | { 0xff, 0x00ef, TDP_COMMON }, |
| 193 | { 0x15, 0x00f8, TDP_COMMON }, |
| 194 | { 0x00, 0x00f9, TDP_COMMON }, |
| 195 | { 0x30, 0x00f0, TDP_COMMON }, |
| 196 | { 0x01, 0x00fd, TDP_COMMON }, |
| 197 | { 0x88, 0x01a1, TDP_COMMON }, |
| 198 | { 0x08, 0x01a2, TDP_COMMON }, |
| 199 | { 0x08, 0x01b1, TDP_COMMON }, |
| 200 | { 0x90, 0x01be, TDP_COMMON }, |
| 201 | { 0x94, 0x0280, TDP_32 }, |
| 202 | { 0x11, 0x0281, TDP_32 }, |
| 203 | { 0x68, 0x0280, TDP_16 }, |
| 204 | { 0x10, 0x0281, TDP_16 }, |
| 205 | { 0x03, 0x0282, TDP_COMMON }, |
| 206 | { 0x0a, 0x0283, TDP_COMMON }, |
| 207 | { 0x80, 0x0284, TDP_COMMON }, |
| 208 | { 0x03, 0x0285, TDP_COMMON }, |
| 209 | { 0xa0, 0x0288, TDP_32 }, |
| 210 | { 0x0f, 0x0289, TDP_32 }, |
| 211 | { 0xd8, 0x0288, TDP_16 }, |
| 212 | { 0x0e, 0x0289, TDP_16 }, |
| 213 | { 0x03, 0x028a, TDP_COMMON }, |
| 214 | { 0x0a, 0x028b, TDP_COMMON }, |
| 215 | { 0x80, 0x028c, TDP_COMMON }, |
| 216 | { 0x03, 0x028d, TDP_COMMON }, |
| 217 | }; |
| 218 | |
| 219 | static const ec_chassis_tdp_t ec_hwm_chassis5[] = { |
| 220 | { 0x33, 0x0005, TDP_COMMON }, |
| 221 | { 0x2f, 0x0018, TDP_COMMON }, |
| 222 | { 0x2f, 0x0019, TDP_COMMON }, |
| 223 | { 0x2f, 0x001a, TDP_COMMON }, |
| 224 | { 0x00, 0x0080, TDP_COMMON }, |
| 225 | { 0x00, 0x0081, TDP_COMMON }, |
| 226 | { 0xbb, 0x0083, TDP_COMMON }, |
| 227 | { 0x89, 0x0085, TDP_32 }, |
| 228 | { 0x99, 0x0085, TDP_16 }, |
| 229 | { 0x9c, 0x0086, TDP_COMMON }, |
| 230 | { 0x39, 0x008a, TDP_32 }, |
| 231 | { 0x42, 0x008a, TDP_16 }, |
| 232 | { 0x6b, 0x008b, TDP_32 }, |
| 233 | { 0x74, 0x008b, TDP_16 }, |
| 234 | { 0x5e, 0x0091, TDP_COMMON }, |
| 235 | { 0x86, 0x0092, TDP_COMMON }, |
| 236 | { 0xa4, 0x0096, TDP_COMMON }, |
| 237 | { 0xa4, 0x0097, TDP_COMMON }, |
| 238 | { 0xa4, 0x0098, TDP_COMMON }, |
| 239 | { 0xa4, 0x009b, TDP_COMMON }, |
| 240 | { 0x0c, 0x00a0, TDP_COMMON }, |
| 241 | { 0x0c, 0x00a1, TDP_COMMON }, |
| 242 | { 0x7c, 0x00ae, TDP_COMMON }, |
| 243 | { 0x7c, 0x00af, TDP_COMMON }, |
| 244 | { 0x9a, 0x00b0, TDP_COMMON }, |
| 245 | { 0x7c, 0x00b3, TDP_COMMON }, |
| 246 | { 0x08, 0x00b6, TDP_COMMON }, |
| 247 | { 0x08, 0x00b7, TDP_COMMON }, |
| 248 | { 0x64, 0x00ea, TDP_COMMON }, |
| 249 | { 0xff, 0x00ef, TDP_COMMON }, |
| 250 | { 0x15, 0x00f8, TDP_COMMON }, |
| 251 | { 0x00, 0x00f9, TDP_COMMON }, |
| 252 | { 0x30, 0x00f0, TDP_COMMON }, |
| 253 | { 0x01, 0x00fd, TDP_COMMON }, |
| 254 | { 0x88, 0x01a1, TDP_COMMON }, |
| 255 | { 0x08, 0x01a2, TDP_COMMON }, |
| 256 | { 0x08, 0x01b1, TDP_COMMON }, |
| 257 | { 0x90, 0x01be, TDP_COMMON }, |
| 258 | { 0x94, 0x0280, TDP_32 }, |
| 259 | { 0x11, 0x0281, TDP_32 }, |
| 260 | { 0x3c, 0x0280, TDP_16 }, |
| 261 | { 0x0f, 0x0281, TDP_16 }, |
| 262 | { 0x03, 0x0282, TDP_COMMON }, |
| 263 | { 0x0a, 0x0283, TDP_COMMON }, |
| 264 | { 0x80, 0x0284, TDP_COMMON }, |
| 265 | { 0x03, 0x0285, TDP_COMMON }, |
| 266 | { 0x60, 0x0288, TDP_32 }, |
| 267 | { 0x09, 0x0289, TDP_32 }, |
| 268 | { 0x98, 0x0288, TDP_16 }, |
| 269 | { 0x08, 0x0289, TDP_16 }, |
| 270 | { 0x03, 0x028a, TDP_COMMON }, |
| 271 | { 0x0a, 0x028b, TDP_COMMON }, |
| 272 | { 0x80, 0x028c, TDP_COMMON }, |
| 273 | { 0x03, 0x028d, TDP_COMMON }, |
| 274 | }; |
| 275 | |
| 276 | static const ec_chassis_tdp_t ec_hwm_chassis6[] = { |
| 277 | { 0x33, 0x0005, TDP_COMMON }, |
| 278 | { 0x2f, 0x0018, TDP_COMMON }, |
| 279 | { 0x2f, 0x0019, TDP_COMMON }, |
| 280 | { 0x2f, 0x001a, TDP_COMMON }, |
| 281 | { 0x00, 0x0080, TDP_COMMON }, |
| 282 | { 0x00, 0x0081, TDP_COMMON }, |
| 283 | { 0xbb, 0x0083, TDP_COMMON }, |
| 284 | { 0x99, 0x0085, TDP_32 }, |
| 285 | { 0x98, 0x0085, TDP_16 }, |
| 286 | { 0xdc, 0x0086, TDP_32 }, |
| 287 | { 0x9c, 0x0086, TDP_16 }, |
| 288 | { 0x3d, 0x008a, TDP_32 }, |
| 289 | { 0x43, 0x008a, TDP_16 }, |
| 290 | { 0x4e, 0x008b, TDP_32 }, |
| 291 | { 0x47, 0x008b, TDP_16 }, |
| 292 | { 0x6d, 0x0090, TDP_COMMON }, |
| 293 | { 0x5f, 0x0091, TDP_32 }, |
| 294 | { 0x61, 0x0091, TDP_16 }, |
| 295 | { 0x86, 0x0092, TDP_COMMON }, |
| 296 | { 0xa4, 0x0096, TDP_COMMON }, |
| 297 | { 0xa4, 0x0097, TDP_COMMON }, |
| 298 | { 0xa4, 0x0098, TDP_COMMON }, |
| 299 | { 0xa4, 0x009b, TDP_COMMON }, |
| 300 | { 0x0e, 0x00a0, TDP_COMMON }, |
| 301 | { 0x0e, 0x00a1, TDP_COMMON }, |
| 302 | { 0x7c, 0x00ae, TDP_COMMON }, |
| 303 | { 0x7c, 0x00af, TDP_COMMON }, |
| 304 | { 0x98, 0x00b0, TDP_32 }, |
| 305 | { 0x9a, 0x00b0, TDP_16 }, |
| 306 | { 0x9a, 0x00b3, TDP_COMMON }, |
| 307 | { 0x08, 0x00b6, TDP_COMMON }, |
| 308 | { 0x08, 0x00b7, TDP_COMMON }, |
| 309 | { 0x64, 0x00ea, TDP_COMMON }, |
| 310 | { 0xff, 0x00ef, TDP_COMMON }, |
| 311 | { 0x15, 0x00f8, TDP_COMMON }, |
| 312 | { 0x00, 0x00f9, TDP_COMMON }, |
| 313 | { 0x30, 0x00f0, TDP_COMMON }, |
| 314 | { 0x01, 0x00fd, TDP_COMMON }, |
| 315 | { 0x88, 0x01a1, TDP_COMMON }, |
| 316 | { 0x08, 0x01a2, TDP_COMMON }, |
| 317 | { 0x08, 0x01b1, TDP_COMMON }, |
| 318 | { 0x97, 0x01be, TDP_32 }, |
| 319 | { 0x95, 0x01be, TDP_16 }, |
| 320 | { 0x68, 0x0280, TDP_32 }, |
| 321 | { 0x10, 0x0281, TDP_32 }, |
| 322 | { 0xd8, 0x0280, TDP_16 }, |
| 323 | { 0x0e, 0x0281, TDP_16 }, |
| 324 | { 0x03, 0x0282, TDP_COMMON }, |
| 325 | { 0x0a, 0x0283, TDP_COMMON }, |
| 326 | { 0x80, 0x0284, TDP_COMMON }, |
| 327 | { 0x03, 0x0285, TDP_COMMON }, |
| 328 | { 0xe4, 0x0288, TDP_32 }, |
| 329 | { 0x0c, 0x0289, TDP_32 }, |
| 330 | { 0x10, 0x0288, TDP_16 }, |
| 331 | { 0x0e, 0x0289, TDP_16 }, |
| 332 | { 0x03, 0x028a, TDP_COMMON }, |
| 333 | { 0x0a, 0x028b, TDP_COMMON }, |
| 334 | { 0x80, 0x028c, TDP_COMMON }, |
| 335 | { 0x03, 0x028d, TDP_COMMON }, |
| 336 | }; |
| 337 | |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 338 | static uint8_t send_mbox_msg_with_int(uint8_t mbox_message) |
| 339 | { |
| 340 | uint8_t int_sts, int_cond; |
| 341 | |
| 342 | sch5545_emi_h2ec_mbox_write(mbox_message); |
| 343 | |
| 344 | do { |
| 345 | int_sts = sch5545_emi_get_int_src_low(); |
| 346 | int_cond = int_sts & 0x71; |
| 347 | } while (int_cond == 0); |
| 348 | |
| 349 | sch5545_emi_set_int_src_low(int_cond); |
| 350 | |
| 351 | if ((int_sts & 1) == 0) |
| 352 | return 0; |
| 353 | |
| 354 | if (sch5545_emi_ec2h_mbox_read() == mbox_message) |
| 355 | return 1; |
| 356 | |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | static uint8_t send_mbox_msg_simple(uint8_t mbox_message) |
| 361 | { |
| 362 | uint8_t int_sts; |
| 363 | |
| 364 | sch5545_emi_h2ec_mbox_write(mbox_message); |
| 365 | |
| 366 | do { |
| 367 | int_sts = sch5545_emi_get_int_src_low(); |
| 368 | if ((int_sts & 70) != 0) |
| 369 | return 0; |
| 370 | } while ((int_sts & 1) == 0); |
| 371 | |
| 372 | if (sch5545_emi_ec2h_mbox_read() == mbox_message) |
| 373 | return 1; |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | static void ec_check_mbox_and_int_status(uint8_t int_src, uint8_t mbox_msg) |
| 379 | { |
| 380 | uint8_t val; |
| 381 | |
| 382 | val = sch5545_emi_ec2h_mbox_read(); |
| 383 | if (val != mbox_msg) |
| 384 | printk(BIOS_SPEW, "EC2H mailbox should be %02x, is %02x\n", mbox_msg, val); |
| 385 | |
| 386 | val = sch5545_emi_get_int_src_low(); |
| 387 | if (val != int_src) |
| 388 | printk(BIOS_SPEW, "EC INT SRC should be %02x, is %02x\n", int_src, val); |
| 389 | |
| 390 | sch5545_emi_set_int_src_low(val); |
| 391 | } |
| 392 | |
| 393 | static uint8_t ec_read_write_reg(uint8_t ldn, uint16_t reg, uint8_t *value, uint8_t rw_bit) |
| 394 | { |
| 395 | uint8_t int_mask_bckup, ret = 0; |
| 396 | rw_bit &= 1; |
| 397 | |
| 398 | int_mask_bckup = sch5545_emi_get_int_mask_low(); |
| 399 | sch5545_emi_set_int_mask_low(0); |
| 400 | |
| 401 | sch5545_emi_ec_write16(0x8000, (ldn << 1) | 0x100 | rw_bit); |
| 402 | if (rw_bit) |
| 403 | sch5545_emi_ec_write32(0x8004, (reg << 16) | *value); |
| 404 | else |
| 405 | sch5545_emi_ec_write32(0x8004, reg << 16); |
| 406 | |
| 407 | ret = send_mbox_msg_with_int(1); |
| 408 | if (ret && !rw_bit) |
| 409 | *value = sch5545_emi_ec_read8(0x8004); |
| 410 | else if (ret != 1 && rw_bit) |
| 411 | printk(BIOS_WARNING, "EC mailbox returned unexpected value " |
| 412 | "when writing %02x to %04x\n", *value, reg); |
| 413 | else if (ret != 1 && !rw_bit) |
| 414 | printk(BIOS_WARNING, "EC mailbox returned unexpected value " |
| 415 | "when reading %04x\n", reg); |
| 416 | |
| 417 | sch5545_emi_set_int_mask_low(int_mask_bckup); |
| 418 | |
| 419 | return ret; |
| 420 | } |
| 421 | |
| 422 | uint16_t sch5545_get_ec_fw_version(void) |
| 423 | { |
John Zhao | 000193a | 2020-09-22 09:52:06 -0700 | [diff] [blame^] | 424 | uint8_t val = 0; |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 425 | uint16_t ec_fw_version; |
| 426 | |
| 427 | /* Read the FW version currently loaded used by EC */ |
| 428 | ec_read_write_reg(EC_HWM_LDN, 0x2ad, &val, READ_OP); |
| 429 | ec_fw_version = (val << 8); |
| 430 | ec_read_write_reg(EC_HWM_LDN, 0x2ae, &val, READ_OP); |
| 431 | ec_fw_version |= val; |
| 432 | ec_read_write_reg(EC_HWM_LDN, 0x2ac, &val, READ_OP); |
| 433 | ec_read_write_reg(EC_HWM_LDN, 0x2fd, &val, READ_OP); |
| 434 | ec_read_write_reg(EC_HWM_LDN, 0x2b0, &val, READ_OP); |
| 435 | |
| 436 | return ec_fw_version; |
| 437 | } |
| 438 | |
| 439 | void sch5545_update_ec_firmware(uint16_t ec_version) |
| 440 | { |
| 441 | uint8_t status; |
| 442 | uint16_t ec_fw_version; |
| 443 | uint32_t *ec_fw_file; |
| 444 | size_t ec_fw_file_size; |
| 445 | |
| 446 | ec_fw_file = cbfs_boot_map_with_leak("sch5545_ecfw.bin", CBFS_TYPE_RAW, |
| 447 | &ec_fw_file_size); |
| 448 | |
| 449 | if (!ec_fw_file || ec_fw_file_size != 0x1750) { |
| 450 | printk(BIOS_ERR, "EC firmware file not found in CBFS!\n"); |
| 451 | printk(BIOS_ERR, "The fans will keep running at maximum speed.\n"); |
| 452 | return; |
| 453 | } |
| 454 | |
| 455 | ec_fw_version = ec_fw_file[3] & 0xffff; |
| 456 | |
| 457 | /* |
| 458 | * After power failure EC loses its configuration. The currently used firmware version |
| 459 | * by EC will be reported as 0x0000. In such case EC firmware needs to be uploaded. |
| 460 | */ |
| 461 | if (ec_version != ec_fw_version) { |
| 462 | printk(BIOS_INFO, "SCH5545 EC is not functional, probably due to power " |
| 463 | "failure\n"); |
| 464 | printk(BIOS_INFO, "Uploading EC firmware (version %04x) to SCH5545\n", |
| 465 | ec_fw_version); |
| 466 | |
| 467 | if (!send_mbox_msg_simple(0x03)) { |
| 468 | printk(BIOS_WARNING, "EC didn't accept FW upload start signal\n"); |
| 469 | printk(BIOS_WARNING, "EC firmware update failed!\n"); |
| 470 | return; |
| 471 | } |
| 472 | |
| 473 | sch5545_emi_ec_write32_bulk(0x8100, ec_fw_file, ec_fw_file_size); |
| 474 | |
| 475 | status = send_mbox_msg_simple(0x04); |
| 476 | status += send_mbox_msg_simple(0x06); |
| 477 | |
| 478 | if (status != 2) |
| 479 | printk(BIOS_WARNING, "EC firmware update failed!\n"); |
| 480 | |
| 481 | if (ec_fw_version != sch5545_get_ec_fw_version()) { |
| 482 | printk(BIOS_ERR, "EC firmware update failed!\n"); |
| 483 | printk(BIOS_ERR, "The fans will keep running at maximum speed\n"); |
| 484 | } else { |
| 485 | printk(BIOS_INFO, "EC firmware update success\n"); |
| 486 | /* |
| 487 | * The vendor BIOS does a full reset after EC firmware update. Most |
| 488 | * likely because the fans are adapting very slowly after automatic fan |
| 489 | * control is enabled. This makes huge noise. To avoid it, also do the |
| 490 | * full reset. On next boot, it will not be necessary. |
| 491 | */ |
| 492 | full_reset(); |
| 493 | } |
| 494 | } else { |
| 495 | printk(BIOS_INFO, "SCH5545 EC firmware up to date (version %04x)\n", |
| 496 | ec_version); |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | void sch5545_ec_hwm_early_init(void) |
| 501 | { |
John Zhao | 000193a | 2020-09-22 09:52:06 -0700 | [diff] [blame^] | 502 | uint8_t val = 0; |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 503 | int i; |
| 504 | |
| 505 | printk(BIOS_DEBUG, "%s\n", __func__); |
| 506 | |
| 507 | ec_check_mbox_and_int_status(0x20, 0x01); |
| 508 | |
| 509 | ec_read_write_reg(2, 0xcb, &val, READ_OP); |
| 510 | ec_read_write_reg(2, 0xb8, &val, READ_OP); |
| 511 | |
| 512 | for (i = 0; i < ARRAY_SIZE(ec_hwm_init_seq); i++) { |
| 513 | val = ec_hwm_init_seq[i].val; |
| 514 | ec_read_write_reg(EC_HWM_LDN, ec_hwm_init_seq[i].reg, &val, |
| 515 | WRITE_OP); |
| 516 | } |
| 517 | |
| 518 | ec_check_mbox_and_int_status(0x01, 0x01); |
| 519 | } |
| 520 | |
| 521 | static uint8_t get_sku_tdp_config(void) |
| 522 | { |
| 523 | msr_t msr; |
| 524 | uint32_t power_unit, tdp; |
| 525 | /* Get units */ |
| 526 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 527 | power_unit = msr.lo & 0xf; |
| 528 | |
| 529 | /* Get power defaults for this SKU */ |
| 530 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 531 | tdp = msr.lo & 0x7fff; |
| 532 | |
| 533 | /* These numbers will determine which settings to use to init EC */ |
| 534 | if ((tdp >> power_unit) < 66) |
| 535 | return 16; |
| 536 | else |
| 537 | return 32; |
| 538 | } |
| 539 | |
| 540 | static uint8_t get_chassis_type(void) |
| 541 | { |
| 542 | uint8_t chassis_id; |
| 543 | |
| 544 | chassis_id = get_gpio(GPIO_CHASSIS_ID0); |
| 545 | chassis_id |= get_gpio(GPIO_CHASSIS_ID1) << 1; |
| 546 | chassis_id |= get_gpio(GPIO_CHASSIS_ID2) << 2; |
| 547 | chassis_id |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3; |
| 548 | |
| 549 | /* This mapping will determine which EC init sequence to use */ |
| 550 | switch (chassis_id) { |
| 551 | case 0x0: |
| 552 | return 5; |
| 553 | case 0x8: |
| 554 | return 4; |
| 555 | case 0x3: |
| 556 | case 0xb: |
| 557 | return 3; |
| 558 | case 0x1: |
| 559 | case 0x9: |
| 560 | case 0x5: |
| 561 | case 0xd: |
| 562 | return 6; |
| 563 | default: |
| 564 | printk(BIOS_DEBUG, "Unknown chassis ID %x\n", chassis_id); |
| 565 | break; |
| 566 | } |
| 567 | |
| 568 | return 0xff; |
| 569 | } |
| 570 | |
| 571 | static void ec_hwm_init_late(const ec_chassis_tdp_t *ec_hwm_sequence, size_t size) |
| 572 | { |
| 573 | unsigned int i; |
| 574 | uint8_t val; |
| 575 | uint8_t tdp_config = get_sku_tdp_config(); |
| 576 | |
| 577 | for (i = 0; i < size; i++) { |
| 578 | if (ec_hwm_sequence[i].tdp == tdp_config || |
| 579 | ec_hwm_sequence[i].tdp == TDP_COMMON) { |
| 580 | val = ec_hwm_sequence[i].val; |
| 581 | ec_read_write_reg(EC_HWM_LDN, ec_hwm_sequence[i].reg, &val, WRITE_OP); |
| 582 | } |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | static void prepare_for_hwm_ec_sequence(uint8_t write_only, uint8_t *value) |
| 587 | { |
| 588 | uint16_t reg; |
| 589 | uint8_t val; |
| 590 | |
| 591 | if (write_only == 1) { |
| 592 | val = *value; |
| 593 | reg = 0x02fc; |
| 594 | } else { |
| 595 | if (value != NULL) |
| 596 | ec_read_write_reg(EC_HWM_LDN, 0x02fc, value, READ_OP); |
| 597 | val = 0xa0; |
| 598 | ec_read_write_reg(EC_HWM_LDN, 0x2fc, &val, WRITE_OP); |
| 599 | val = 0x32; |
| 600 | reg = 0x02fd; |
| 601 | } |
| 602 | |
| 603 | ec_read_write_reg(1, reg, &val, WRITE_OP); |
| 604 | } |
| 605 | |
| 606 | void sch5545_ec_hwm_init(void *unused) |
| 607 | { |
John Zhao | 000193a | 2020-09-22 09:52:06 -0700 | [diff] [blame^] | 608 | uint8_t val = 0, val_2fc, chassis_type, fan_speed_full = 0; |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 609 | |
| 610 | printk(BIOS_DEBUG, "%s\n", __func__); |
| 611 | sch5545_emi_init(0x2e); |
| 612 | |
| 613 | chassis_type = get_chassis_type(); |
| 614 | |
| 615 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); |
| 616 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); |
| 617 | ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP); |
| 618 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); |
| 619 | val |= 0x02; |
| 620 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); |
| 621 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); |
| 622 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); |
| 623 | ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP); |
| 624 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); |
| 625 | val |= 0x04; |
| 626 | ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); |
| 627 | ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP); |
| 628 | ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); |
| 629 | |
| 630 | ec_check_mbox_and_int_status(0x00, 0x01); |
| 631 | |
| 632 | prepare_for_hwm_ec_sequence(0, &val_2fc); |
| 633 | |
| 634 | if (chassis_type != 0xff) { |
| 635 | printk(BIOS_DEBUG, "Performing HWM init for chassis %d\n", chassis_type); |
| 636 | switch (chassis_type) { |
| 637 | case 3: |
| 638 | ec_hwm_init_late(ec_hwm_chassis3, ARRAY_SIZE(ec_hwm_chassis3)); |
| 639 | break; |
| 640 | case 4: |
| 641 | ec_hwm_init_late(ec_hwm_chassis4, ARRAY_SIZE(ec_hwm_chassis4)); |
| 642 | break; |
| 643 | case 5: |
| 644 | ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis5)); |
| 645 | break; |
| 646 | case 6: |
| 647 | ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis6)); |
| 648 | break; |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | if (CONFIG_MAX_CPUS > 2) { |
| 653 | val = 0x30; |
| 654 | ec_read_write_reg(EC_HWM_LDN, 0x009e, &val, WRITE_OP); |
| 655 | ec_read_write_reg(EC_HWM_LDN, 0x00ea, &val, READ_OP); |
| 656 | ec_read_write_reg(EC_HWM_LDN, 0x00eb, &val, WRITE_OP); |
| 657 | } |
| 658 | |
| 659 | ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP); |
| 660 | |
| 661 | if (get_option(&fan_speed_full, "fan_full_speed") != CB_SUCCESS) |
| 662 | printk(BIOS_INFO, "fan_full_speed CMOS option not found. " |
| 663 | "Fans will be set up for automatic control\n"); |
| 664 | |
| 665 | if (fan_speed_full) { |
| 666 | ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP); |
| 667 | val |= 0x60; |
| 668 | ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, WRITE_OP); |
| 669 | ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP); |
| 670 | val |= 0x60; |
| 671 | ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, WRITE_OP); |
| 672 | } |
| 673 | |
| 674 | ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP); |
| 675 | |
| 676 | if (chassis_type == 4 || chassis_type == 5) { |
| 677 | ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, READ_OP); |
| 678 | val &= 0xfb; |
| 679 | ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, WRITE_OP); |
| 680 | ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, READ_OP); |
| 681 | val &= 0xfb; |
| 682 | ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, WRITE_OP); |
| 683 | ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, READ_OP); |
| 684 | val &= 0xfb; |
| 685 | ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, WRITE_OP); |
| 686 | val = 0x99; |
| 687 | ec_read_write_reg(EC_HWM_LDN, 0x008a, &val, WRITE_OP); |
| 688 | val = 0x47; |
| 689 | ec_read_write_reg(EC_HWM_LDN, 0x008b, &val, WRITE_OP); |
| 690 | val = 0x91; |
| 691 | ec_read_write_reg(EC_HWM_LDN, 0x008c, &val, WRITE_OP); |
| 692 | } |
| 693 | |
| 694 | ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); |
| 695 | val &= 0xf7; |
| 696 | ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP); |
| 697 | |
| 698 | val = 0x6a; |
| 699 | if (chassis_type != 3) |
| 700 | ec_read_write_reg(EC_HWM_LDN, 0x0059, &val, WRITE_OP); |
| 701 | else |
| 702 | ec_read_write_reg(EC_HWM_LDN, 0x0057, &val, WRITE_OP); |
| 703 | |
| 704 | ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, READ_OP); |
| 705 | val |= 0x40; |
| 706 | ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, WRITE_OP); |
| 707 | |
| 708 | if (chassis_type == 3) { |
| 709 | ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); |
| 710 | val |= 0x04; |
| 711 | } else { |
| 712 | ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); |
| 713 | val |= 0x08; |
| 714 | } |
| 715 | ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP); |
| 716 | |
| 717 | val = 0x0e; |
| 718 | ec_read_write_reg(EC_HWM_LDN, 0x007b, &val, WRITE_OP); |
| 719 | ec_read_write_reg(EC_HWM_LDN, 0x007c, &val, WRITE_OP); |
| 720 | val = 0x01; |
| 721 | ec_read_write_reg(EC_HWM_LDN, 0x007a, &val, WRITE_OP); |
| 722 | } |