blob: 401345254da40442895bb092699fb419eb8dbc6c [file] [log] [blame]
Michał Żygowski72f06ca2020-04-13 21:42:24 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <cbfs.h>
4#include <cf9_reset.h>
5#include <string.h>
6#include <option.h>
7#include <arch/io.h>
8#include <cpu/x86/msr.h>
9#include <console/console.h>
10#include <cpu/intel/model_206ax/model_206ax.h>
11#include <southbridge/intel/common/gpio.h>
12#include <superio/smsc/sch5545/sch5545.h>
13#include <superio/smsc/sch5545/sch5545_emi.h>
14
15#include "sch5545_ec.h"
16
17#define GPIO_CHASSIS_ID0 1
18#define GPIO_CHASSIS_ID1 17
19#define GPIO_CHASSIS_ID2 37
20#define GPIO_FRONT_PANEL_CHASSIS_DET_L 70
21
22enum {
23 TDP_16 = 0x10,
24 TDP_32 = 0x20,
25 TDP_COMMON = 0xff,
26};
27
28typedef struct ec_val_reg_tdp {
29 uint8_t val;
30 uint16_t reg;
31 uint8_t tdp;
32} ec_chassis_tdp_t;
33
34static const struct ec_val_reg ec_hwm_init_seq[] = {
35 { 0xa0, 0x02fc },
36 { 0x32, 0x02fd },
37 { 0x77, 0x0005 },
38 { 0x0f, 0x0018 },
39 { 0x2f, 0x0019 },
40 { 0x2f, 0x001a },
41 { 0x33, 0x008a },
42 { 0x33, 0x008b },
43 { 0x33, 0x008c },
44 { 0x10, 0x00ba },
45 { 0xff, 0x00d1 },
46 { 0xff, 0x00d6 },
47 { 0xff, 0x00db },
48 { 0x00, 0x0048 },
49 { 0x00, 0x0049 },
50 { 0x00, 0x007a },
51 { 0x00, 0x007b },
52 { 0x00, 0x007c },
53 { 0x00, 0x0080 },
54 { 0x00, 0x0081 },
55 { 0x00, 0x0082 },
56 { 0xbb, 0x0083 },
57 { 0xb0, 0x0084 },
58 { 0x88, 0x01a1 },
59 { 0x80, 0x01a4 },
60 { 0x00, 0x0088 },
61 { 0x00, 0x0089 },
62 { 0x02, 0x00a0 },
63 { 0x02, 0x00a1 },
64 { 0x02, 0x00a2 },
65 { 0x04, 0x00a4 },
66 { 0x04, 0x00a5 },
67 { 0x04, 0x00a6 },
68 { 0x00, 0x00ab },
69 { 0x3f, 0x00ad },
70 { 0x07, 0x00b7 },
71 { 0x50, 0x0062 },
72 { 0x46, 0x0063 },
73 { 0x50, 0x0064 },
74 { 0x46, 0x0065 },
75 { 0x50, 0x0066 },
76 { 0x46, 0x0067 },
77 { 0x98, 0x0057 },
78 { 0x98, 0x0059 },
79 { 0x7c, 0x0061 },
80 { 0x00, 0x01bc },
81 { 0x00, 0x01bd },
82 { 0x00, 0x01bb },
83 { 0xdd, 0x0085 },
84 { 0xdd, 0x0086 },
85 { 0x07, 0x0087 },
86 { 0x5e, 0x0090 },
87 { 0x5e, 0x0091 },
88 { 0x5d, 0x0095 },
89 { 0x00, 0x0096 },
90 { 0x00, 0x0097 },
91 { 0x00, 0x009b },
92 { 0x86, 0x00ae },
93 { 0x86, 0x00af },
94 { 0x67, 0x00b3 },
95 { 0xff, 0x00c4 },
96 { 0xff, 0x00c5 },
97 { 0xff, 0x00c9 },
98 { 0x01, 0x0040 },
99 { 0x00, 0x02fc },
100 { 0x9a, 0x02b3 },
101 { 0x05, 0x02b4 },
102 { 0x01, 0x02cc },
103 { 0x4c, 0x02d0 },
104 { 0x01, 0x02d2 },
105 { 0x01, 0x006f },
106 { 0x02, 0x0070 },
107 { 0x03, 0x0071 },
108};
109
110
111static const ec_chassis_tdp_t ec_hwm_chassis3[] = {
112 { 0x33, 0x0005, TDP_COMMON },
113 { 0x2f, 0x0018, TDP_COMMON },
114 { 0x2f, 0x0019, TDP_COMMON },
115 { 0x2f, 0x001a, TDP_COMMON },
116 { 0x00, 0x0080, TDP_COMMON },
117 { 0x00, 0x0081, TDP_COMMON },
118 { 0xbb, 0x0083, TDP_COMMON },
119 { 0x8a, 0x0085, TDP_16 },
120 { 0x2c, 0x0086, TDP_16 },
121 { 0x66, 0x008a, TDP_16 },
122 { 0x5b, 0x008b, TDP_16 },
123 { 0x65, 0x0090, TDP_COMMON },
124 { 0x70, 0x0091, TDP_COMMON },
125 { 0x86, 0x0092, TDP_COMMON },
126 { 0xa4, 0x0096, TDP_COMMON },
127 { 0xa4, 0x0097, TDP_COMMON },
128 { 0xa4, 0x0098, TDP_COMMON },
129 { 0xa4, 0x009b, TDP_COMMON },
130 { 0x0e, 0x00a0, TDP_COMMON },
131 { 0x0e, 0x00a1, TDP_COMMON },
132 { 0x7c, 0x00ae, TDP_COMMON },
133 { 0x86, 0x00af, TDP_COMMON },
134 { 0x95, 0x00b0, TDP_COMMON },
135 { 0x9a, 0x00b3, TDP_COMMON },
136 { 0x08, 0x00b6, TDP_COMMON },
137 { 0x08, 0x00b7, TDP_COMMON },
138 { 0x64, 0x00ea, TDP_COMMON },
139 { 0xff, 0x00ef, TDP_COMMON },
140 { 0x15, 0x00f8, TDP_COMMON },
141 { 0x00, 0x00f9, TDP_COMMON },
142 { 0x30, 0x00f0, TDP_COMMON },
143 { 0x01, 0x00fd, TDP_COMMON },
144 { 0x88, 0x01a1, TDP_COMMON },
145 { 0x08, 0x01a2, TDP_COMMON },
146 { 0x08, 0x01b1, TDP_COMMON },
147 { 0x94, 0x01be, TDP_COMMON },
148 { 0x94, 0x0280, TDP_16 },
149 { 0x11, 0x0281, TDP_16 },
150 { 0x03, 0x0282, TDP_COMMON },
151 { 0x0a, 0x0283, TDP_COMMON },
152 { 0x80, 0x0284, TDP_COMMON },
153 { 0x03, 0x0285, TDP_COMMON },
154 { 0x68, 0x0288, TDP_16 },
155 { 0x10, 0x0289, TDP_16 },
156 { 0x03, 0x028a, TDP_COMMON },
157 { 0x0a, 0x028b, TDP_COMMON },
158 { 0x80, 0x028c, TDP_COMMON },
159 { 0x03, 0x028d, TDP_COMMON },
160};
161
162static const ec_chassis_tdp_t ec_hwm_chassis4[] = {
163 { 0x33, 0x0005, TDP_COMMON },
164 { 0x2f, 0x0018, TDP_COMMON },
165 { 0x2f, 0x0019, TDP_COMMON },
166 { 0x2f, 0x001a, TDP_COMMON },
167 { 0x00, 0x0080, TDP_COMMON },
168 { 0x00, 0x0081, TDP_COMMON },
169 { 0xbb, 0x0083, TDP_COMMON },
170 { 0x99, 0x0085, TDP_32 },
171 { 0x98, 0x0085, TDP_16 },
172 { 0xbc, 0x0086, TDP_32 },
173 { 0x1c, 0x0086, TDP_16 },
174 { 0x39, 0x008a, TDP_32 },
175 { 0x3d, 0x008a, TDP_16 },
176 { 0x40, 0x008b, TDP_32 },
177 { 0x43, 0x008b, TDP_16 },
178 { 0x68, 0x0090, TDP_COMMON },
179 { 0x5e, 0x0091, TDP_COMMON },
180 { 0x86, 0x0092, TDP_COMMON },
181 { 0xa4, 0x0096, TDP_COMMON },
182 { 0xa4, 0x0097, TDP_COMMON },
183 { 0xa4, 0x0098, TDP_COMMON },
184 { 0xa4, 0x009b, TDP_COMMON },
185 { 0x0c, 0x00a0, TDP_COMMON },
186 { 0x0c, 0x00a1, TDP_COMMON },
187 { 0x72, 0x00ae, TDP_COMMON },
188 { 0x7c, 0x00af, TDP_COMMON },
189 { 0x9a, 0x00b0, TDP_COMMON },
190 { 0x7c, 0x00b3, TDP_COMMON },
191 { 0x08, 0x00b6, TDP_COMMON },
192 { 0x08, 0x00b7, TDP_COMMON },
193 { 0x64, 0x00ea, TDP_COMMON },
194 { 0xff, 0x00ef, TDP_COMMON },
195 { 0x15, 0x00f8, TDP_COMMON },
196 { 0x00, 0x00f9, TDP_COMMON },
197 { 0x30, 0x00f0, TDP_COMMON },
198 { 0x01, 0x00fd, TDP_COMMON },
199 { 0x88, 0x01a1, TDP_COMMON },
200 { 0x08, 0x01a2, TDP_COMMON },
201 { 0x08, 0x01b1, TDP_COMMON },
202 { 0x90, 0x01be, TDP_COMMON },
203 { 0x94, 0x0280, TDP_32 },
204 { 0x11, 0x0281, TDP_32 },
205 { 0x68, 0x0280, TDP_16 },
206 { 0x10, 0x0281, TDP_16 },
207 { 0x03, 0x0282, TDP_COMMON },
208 { 0x0a, 0x0283, TDP_COMMON },
209 { 0x80, 0x0284, TDP_COMMON },
210 { 0x03, 0x0285, TDP_COMMON },
211 { 0xa0, 0x0288, TDP_32 },
212 { 0x0f, 0x0289, TDP_32 },
213 { 0xd8, 0x0288, TDP_16 },
214 { 0x0e, 0x0289, TDP_16 },
215 { 0x03, 0x028a, TDP_COMMON },
216 { 0x0a, 0x028b, TDP_COMMON },
217 { 0x80, 0x028c, TDP_COMMON },
218 { 0x03, 0x028d, TDP_COMMON },
219};
220
221static const ec_chassis_tdp_t ec_hwm_chassis5[] = {
222 { 0x33, 0x0005, TDP_COMMON },
223 { 0x2f, 0x0018, TDP_COMMON },
224 { 0x2f, 0x0019, TDP_COMMON },
225 { 0x2f, 0x001a, TDP_COMMON },
226 { 0x00, 0x0080, TDP_COMMON },
227 { 0x00, 0x0081, TDP_COMMON },
228 { 0xbb, 0x0083, TDP_COMMON },
229 { 0x89, 0x0085, TDP_32 },
230 { 0x99, 0x0085, TDP_16 },
231 { 0x9c, 0x0086, TDP_COMMON },
232 { 0x39, 0x008a, TDP_32 },
233 { 0x42, 0x008a, TDP_16 },
234 { 0x6b, 0x008b, TDP_32 },
235 { 0x74, 0x008b, TDP_16 },
236 { 0x5e, 0x0091, TDP_COMMON },
237 { 0x86, 0x0092, TDP_COMMON },
238 { 0xa4, 0x0096, TDP_COMMON },
239 { 0xa4, 0x0097, TDP_COMMON },
240 { 0xa4, 0x0098, TDP_COMMON },
241 { 0xa4, 0x009b, TDP_COMMON },
242 { 0x0c, 0x00a0, TDP_COMMON },
243 { 0x0c, 0x00a1, TDP_COMMON },
244 { 0x7c, 0x00ae, TDP_COMMON },
245 { 0x7c, 0x00af, TDP_COMMON },
246 { 0x9a, 0x00b0, TDP_COMMON },
247 { 0x7c, 0x00b3, TDP_COMMON },
248 { 0x08, 0x00b6, TDP_COMMON },
249 { 0x08, 0x00b7, TDP_COMMON },
250 { 0x64, 0x00ea, TDP_COMMON },
251 { 0xff, 0x00ef, TDP_COMMON },
252 { 0x15, 0x00f8, TDP_COMMON },
253 { 0x00, 0x00f9, TDP_COMMON },
254 { 0x30, 0x00f0, TDP_COMMON },
255 { 0x01, 0x00fd, TDP_COMMON },
256 { 0x88, 0x01a1, TDP_COMMON },
257 { 0x08, 0x01a2, TDP_COMMON },
258 { 0x08, 0x01b1, TDP_COMMON },
259 { 0x90, 0x01be, TDP_COMMON },
260 { 0x94, 0x0280, TDP_32 },
261 { 0x11, 0x0281, TDP_32 },
262 { 0x3c, 0x0280, TDP_16 },
263 { 0x0f, 0x0281, TDP_16 },
264 { 0x03, 0x0282, TDP_COMMON },
265 { 0x0a, 0x0283, TDP_COMMON },
266 { 0x80, 0x0284, TDP_COMMON },
267 { 0x03, 0x0285, TDP_COMMON },
268 { 0x60, 0x0288, TDP_32 },
269 { 0x09, 0x0289, TDP_32 },
270 { 0x98, 0x0288, TDP_16 },
271 { 0x08, 0x0289, TDP_16 },
272 { 0x03, 0x028a, TDP_COMMON },
273 { 0x0a, 0x028b, TDP_COMMON },
274 { 0x80, 0x028c, TDP_COMMON },
275 { 0x03, 0x028d, TDP_COMMON },
276};
277
278static const ec_chassis_tdp_t ec_hwm_chassis6[] = {
279 { 0x33, 0x0005, TDP_COMMON },
280 { 0x2f, 0x0018, TDP_COMMON },
281 { 0x2f, 0x0019, TDP_COMMON },
282 { 0x2f, 0x001a, TDP_COMMON },
283 { 0x00, 0x0080, TDP_COMMON },
284 { 0x00, 0x0081, TDP_COMMON },
285 { 0xbb, 0x0083, TDP_COMMON },
286 { 0x99, 0x0085, TDP_32 },
287 { 0x98, 0x0085, TDP_16 },
288 { 0xdc, 0x0086, TDP_32 },
289 { 0x9c, 0x0086, TDP_16 },
290 { 0x3d, 0x008a, TDP_32 },
291 { 0x43, 0x008a, TDP_16 },
292 { 0x4e, 0x008b, TDP_32 },
293 { 0x47, 0x008b, TDP_16 },
294 { 0x6d, 0x0090, TDP_COMMON },
295 { 0x5f, 0x0091, TDP_32 },
296 { 0x61, 0x0091, TDP_16 },
297 { 0x86, 0x0092, TDP_COMMON },
298 { 0xa4, 0x0096, TDP_COMMON },
299 { 0xa4, 0x0097, TDP_COMMON },
300 { 0xa4, 0x0098, TDP_COMMON },
301 { 0xa4, 0x009b, TDP_COMMON },
302 { 0x0e, 0x00a0, TDP_COMMON },
303 { 0x0e, 0x00a1, TDP_COMMON },
304 { 0x7c, 0x00ae, TDP_COMMON },
305 { 0x7c, 0x00af, TDP_COMMON },
306 { 0x98, 0x00b0, TDP_32 },
307 { 0x9a, 0x00b0, TDP_16 },
308 { 0x9a, 0x00b3, TDP_COMMON },
309 { 0x08, 0x00b6, TDP_COMMON },
310 { 0x08, 0x00b7, TDP_COMMON },
311 { 0x64, 0x00ea, TDP_COMMON },
312 { 0xff, 0x00ef, TDP_COMMON },
313 { 0x15, 0x00f8, TDP_COMMON },
314 { 0x00, 0x00f9, TDP_COMMON },
315 { 0x30, 0x00f0, TDP_COMMON },
316 { 0x01, 0x00fd, TDP_COMMON },
317 { 0x88, 0x01a1, TDP_COMMON },
318 { 0x08, 0x01a2, TDP_COMMON },
319 { 0x08, 0x01b1, TDP_COMMON },
320 { 0x97, 0x01be, TDP_32 },
321 { 0x95, 0x01be, TDP_16 },
322 { 0x68, 0x0280, TDP_32 },
323 { 0x10, 0x0281, TDP_32 },
324 { 0xd8, 0x0280, TDP_16 },
325 { 0x0e, 0x0281, TDP_16 },
326 { 0x03, 0x0282, TDP_COMMON },
327 { 0x0a, 0x0283, TDP_COMMON },
328 { 0x80, 0x0284, TDP_COMMON },
329 { 0x03, 0x0285, TDP_COMMON },
330 { 0xe4, 0x0288, TDP_32 },
331 { 0x0c, 0x0289, TDP_32 },
332 { 0x10, 0x0288, TDP_16 },
333 { 0x0e, 0x0289, TDP_16 },
334 { 0x03, 0x028a, TDP_COMMON },
335 { 0x0a, 0x028b, TDP_COMMON },
336 { 0x80, 0x028c, TDP_COMMON },
337 { 0x03, 0x028d, TDP_COMMON },
338};
339
340
341
342static uint8_t send_mbox_msg_with_int(uint8_t mbox_message)
343{
344 uint8_t int_sts, int_cond;
345
346 sch5545_emi_h2ec_mbox_write(mbox_message);
347
348 do {
349 int_sts = sch5545_emi_get_int_src_low();
350 int_cond = int_sts & 0x71;
351 } while (int_cond == 0);
352
353 sch5545_emi_set_int_src_low(int_cond);
354
355 if ((int_sts & 1) == 0)
356 return 0;
357
358 if (sch5545_emi_ec2h_mbox_read() == mbox_message)
359 return 1;
360
361 return 0;
362}
363
364static uint8_t send_mbox_msg_simple(uint8_t mbox_message)
365{
366 uint8_t int_sts;
367
368 sch5545_emi_h2ec_mbox_write(mbox_message);
369
370 do {
371 int_sts = sch5545_emi_get_int_src_low();
372 if ((int_sts & 70) != 0)
373 return 0;
374 } while ((int_sts & 1) == 0);
375
376 if (sch5545_emi_ec2h_mbox_read() == mbox_message)
377 return 1;
378
379 return 0;
380}
381
382static void ec_check_mbox_and_int_status(uint8_t int_src, uint8_t mbox_msg)
383{
384 uint8_t val;
385
386 val = sch5545_emi_ec2h_mbox_read();
387 if (val != mbox_msg)
388 printk(BIOS_SPEW, "EC2H mailbox should be %02x, is %02x\n", mbox_msg, val);
389
390 val = sch5545_emi_get_int_src_low();
391 if (val != int_src)
392 printk(BIOS_SPEW, "EC INT SRC should be %02x, is %02x\n", int_src, val);
393
394 sch5545_emi_set_int_src_low(val);
395}
396
397static uint8_t ec_read_write_reg(uint8_t ldn, uint16_t reg, uint8_t *value, uint8_t rw_bit)
398{
399 uint8_t int_mask_bckup, ret = 0;
400 rw_bit &= 1;
401
402 int_mask_bckup = sch5545_emi_get_int_mask_low();
403 sch5545_emi_set_int_mask_low(0);
404
405 sch5545_emi_ec_write16(0x8000, (ldn << 1) | 0x100 | rw_bit);
406 if (rw_bit)
407 sch5545_emi_ec_write32(0x8004, (reg << 16) | *value);
408 else
409 sch5545_emi_ec_write32(0x8004, reg << 16);
410
411 ret = send_mbox_msg_with_int(1);
412 if (ret && !rw_bit)
413 *value = sch5545_emi_ec_read8(0x8004);
414 else if (ret != 1 && rw_bit)
415 printk(BIOS_WARNING, "EC mailbox returned unexpected value "
416 "when writing %02x to %04x\n", *value, reg);
417 else if (ret != 1 && !rw_bit)
418 printk(BIOS_WARNING, "EC mailbox returned unexpected value "
419 "when reading %04x\n", reg);
420
421 sch5545_emi_set_int_mask_low(int_mask_bckup);
422
423 return ret;
424}
425
426uint16_t sch5545_get_ec_fw_version(void)
427{
428 uint8_t val;
429 uint16_t ec_fw_version;
430
431 /* Read the FW version currently loaded used by EC */
432 ec_read_write_reg(EC_HWM_LDN, 0x2ad, &val, READ_OP);
433 ec_fw_version = (val << 8);
434 ec_read_write_reg(EC_HWM_LDN, 0x2ae, &val, READ_OP);
435 ec_fw_version |= val;
436 ec_read_write_reg(EC_HWM_LDN, 0x2ac, &val, READ_OP);
437 ec_read_write_reg(EC_HWM_LDN, 0x2fd, &val, READ_OP);
438 ec_read_write_reg(EC_HWM_LDN, 0x2b0, &val, READ_OP);
439
440 return ec_fw_version;
441}
442
443void sch5545_update_ec_firmware(uint16_t ec_version)
444{
445 uint8_t status;
446 uint16_t ec_fw_version;
447 uint32_t *ec_fw_file;
448 size_t ec_fw_file_size;
449
450 ec_fw_file = cbfs_boot_map_with_leak("sch5545_ecfw.bin", CBFS_TYPE_RAW,
451 &ec_fw_file_size);
452
453 if (!ec_fw_file || ec_fw_file_size != 0x1750) {
454 printk(BIOS_ERR, "EC firmware file not found in CBFS!\n");
455 printk(BIOS_ERR, "The fans will keep running at maximum speed.\n");
456 return;
457 }
458
459 ec_fw_version = ec_fw_file[3] & 0xffff;
460
461 /*
462 * After power failure EC loses its configuration. The currently used firmware version
463 * by EC will be reported as 0x0000. In such case EC firmware needs to be uploaded.
464 */
465 if (ec_version != ec_fw_version) {
466 printk(BIOS_INFO, "SCH5545 EC is not functional, probably due to power "
467 "failure\n");
468 printk(BIOS_INFO, "Uploading EC firmware (version %04x) to SCH5545\n",
469 ec_fw_version);
470
471 if (!send_mbox_msg_simple(0x03)) {
472 printk(BIOS_WARNING, "EC didn't accept FW upload start signal\n");
473 printk(BIOS_WARNING, "EC firmware update failed!\n");
474 return;
475 }
476
477 sch5545_emi_ec_write32_bulk(0x8100, ec_fw_file, ec_fw_file_size);
478
479 status = send_mbox_msg_simple(0x04);
480 status += send_mbox_msg_simple(0x06);
481
482 if (status != 2)
483 printk(BIOS_WARNING, "EC firmware update failed!\n");
484
485 if (ec_fw_version != sch5545_get_ec_fw_version()) {
486 printk(BIOS_ERR, "EC firmware update failed!\n");
487 printk(BIOS_ERR, "The fans will keep running at maximum speed\n");
488 } else {
489 printk(BIOS_INFO, "EC firmware update success\n");
490 /*
491 * The vendor BIOS does a full reset after EC firmware update. Most
492 * likely because the fans are adapting very slowly after automatic fan
493 * control is enabled. This makes huge noise. To avoid it, also do the
494 * full reset. On next boot, it will not be necessary.
495 */
496 full_reset();
497 }
498 } else {
499 printk(BIOS_INFO, "SCH5545 EC firmware up to date (version %04x)\n",
500 ec_version);
501 }
502}
503
504void sch5545_ec_hwm_early_init(void)
505{
506 uint8_t val;
507 int i;
508
509 printk(BIOS_DEBUG, "%s\n", __func__);
510
511 ec_check_mbox_and_int_status(0x20, 0x01);
512
513 ec_read_write_reg(2, 0xcb, &val, READ_OP);
514 ec_read_write_reg(2, 0xb8, &val, READ_OP);
515
516 for (i = 0; i < ARRAY_SIZE(ec_hwm_init_seq); i++) {
517 val = ec_hwm_init_seq[i].val;
518 ec_read_write_reg(EC_HWM_LDN, ec_hwm_init_seq[i].reg, &val,
519 WRITE_OP);
520 }
521
522 ec_check_mbox_and_int_status(0x01, 0x01);
523}
524
525static uint8_t get_sku_tdp_config(void)
526{
527 msr_t msr;
528 uint32_t power_unit, tdp;
529 /* Get units */
530 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
531 power_unit = msr.lo & 0xf;
532
533 /* Get power defaults for this SKU */
534 msr = rdmsr(MSR_PKG_POWER_SKU);
535 tdp = msr.lo & 0x7fff;
536
537 /* These numbers will determine which settings to use to init EC */
538 if ((tdp >> power_unit) < 66)
539 return 16;
540 else
541 return 32;
542}
543
544static uint8_t get_chassis_type(void)
545{
546 uint8_t chassis_id;
547
548 chassis_id = get_gpio(GPIO_CHASSIS_ID0);
549 chassis_id |= get_gpio(GPIO_CHASSIS_ID1) << 1;
550 chassis_id |= get_gpio(GPIO_CHASSIS_ID2) << 2;
551 chassis_id |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
552
553 /* This mapping will determine which EC init sequence to use */
554 switch (chassis_id) {
555 case 0x0:
556 return 5;
557 case 0x8:
558 return 4;
559 case 0x3:
560 case 0xb:
561 return 3;
562 case 0x1:
563 case 0x9:
564 case 0x5:
565 case 0xd:
566 return 6;
567 default:
568 printk(BIOS_DEBUG, "Unknown chassis ID %x\n", chassis_id);
569 break;
570 }
571
572 return 0xff;
573}
574
575static void ec_hwm_init_late(const ec_chassis_tdp_t *ec_hwm_sequence, size_t size)
576{
577 unsigned int i;
578 uint8_t val;
579 uint8_t tdp_config = get_sku_tdp_config();
580
581 for (i = 0; i < size; i++) {
582 if (ec_hwm_sequence[i].tdp == tdp_config ||
583 ec_hwm_sequence[i].tdp == TDP_COMMON) {
584 val = ec_hwm_sequence[i].val;
585 ec_read_write_reg(EC_HWM_LDN, ec_hwm_sequence[i].reg, &val, WRITE_OP);
586 }
587 }
588}
589
590static void prepare_for_hwm_ec_sequence(uint8_t write_only, uint8_t *value)
591{
592 uint16_t reg;
593 uint8_t val;
594
595 if (write_only == 1) {
596 val = *value;
597 reg = 0x02fc;
598 } else {
599 if (value != NULL)
600 ec_read_write_reg(EC_HWM_LDN, 0x02fc, value, READ_OP);
601 val = 0xa0;
602 ec_read_write_reg(EC_HWM_LDN, 0x2fc, &val, WRITE_OP);
603 val = 0x32;
604 reg = 0x02fd;
605 }
606
607 ec_read_write_reg(1, reg, &val, WRITE_OP);
608}
609
610void sch5545_ec_hwm_init(void *unused)
611{
612 uint8_t val, val_2fc, chassis_type, fan_speed_full = 0;
613
614 printk(BIOS_DEBUG, "%s\n", __func__);
615 sch5545_emi_init(0x2e);
616
617 chassis_type = get_chassis_type();
618
619 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
620 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
621 ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP);
622 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
623 val |= 0x02;
624 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
625 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
626 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
627 ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP);
628 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
629 val |= 0x04;
630 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
631 ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP);
632 ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP);
633
634 ec_check_mbox_and_int_status(0x00, 0x01);
635
636 prepare_for_hwm_ec_sequence(0, &val_2fc);
637
638 if (chassis_type != 0xff) {
639 printk(BIOS_DEBUG, "Performing HWM init for chassis %d\n", chassis_type);
640 switch (chassis_type) {
641 case 3:
642 ec_hwm_init_late(ec_hwm_chassis3, ARRAY_SIZE(ec_hwm_chassis3));
643 break;
644 case 4:
645 ec_hwm_init_late(ec_hwm_chassis4, ARRAY_SIZE(ec_hwm_chassis4));
646 break;
647 case 5:
648 ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis5));
649 break;
650 case 6:
651 ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis6));
652 break;
653 }
654 }
655
656 if (CONFIG_MAX_CPUS > 2) {
657 val = 0x30;
658 ec_read_write_reg(EC_HWM_LDN, 0x009e, &val, WRITE_OP);
659 ec_read_write_reg(EC_HWM_LDN, 0x00ea, &val, READ_OP);
660 ec_read_write_reg(EC_HWM_LDN, 0x00eb, &val, WRITE_OP);
661 }
662
663 ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP);
664
665 if (get_option(&fan_speed_full, "fan_full_speed") != CB_SUCCESS)
666 printk(BIOS_INFO, "fan_full_speed CMOS option not found. "
667 "Fans will be set up for automatic control\n");
668
669 if (fan_speed_full) {
670 ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP);
671 val |= 0x60;
672 ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, WRITE_OP);
673 ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP);
674 val |= 0x60;
675 ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, WRITE_OP);
676 }
677
678 ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP);
679
680 if (chassis_type == 4 || chassis_type == 5) {
681 ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, READ_OP);
682 val &= 0xfb;
683 ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, WRITE_OP);
684 ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, READ_OP);
685 val &= 0xfb;
686 ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, WRITE_OP);
687 ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, READ_OP);
688 val &= 0xfb;
689 ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, WRITE_OP);
690 val = 0x99;
691 ec_read_write_reg(EC_HWM_LDN, 0x008a, &val, WRITE_OP);
692 val = 0x47;
693 ec_read_write_reg(EC_HWM_LDN, 0x008b, &val, WRITE_OP);
694 val = 0x91;
695 ec_read_write_reg(EC_HWM_LDN, 0x008c, &val, WRITE_OP);
696 }
697
698 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP);
699 val &= 0xf7;
700 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP);
701
702 val = 0x6a;
703 if (chassis_type != 3)
704 ec_read_write_reg(EC_HWM_LDN, 0x0059, &val, WRITE_OP);
705 else
706 ec_read_write_reg(EC_HWM_LDN, 0x0057, &val, WRITE_OP);
707
708 ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, READ_OP);
709 val |= 0x40;
710 ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, WRITE_OP);
711
712 if (chassis_type == 3) {
713 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP);
714 val |= 0x04;
715 } else {
716 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP);
717 val |= 0x08;
718 }
719 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP);
720
721 val = 0x0e;
722 ec_read_write_reg(EC_HWM_LDN, 0x007b, &val, WRITE_OP);
723 ec_read_write_reg(EC_HWM_LDN, 0x007c, &val, WRITE_OP);
724 val = 0x01;
725 ec_read_write_reg(EC_HWM_LDN, 0x007a, &val, WRITE_OP);
726}