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review.coreboot.org / coreboot / fbdb085549b6c500e12dc2fb21143a197b4be042 / src / northbridge / intel / sandybridge
  1. fbdb085 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT by Kyösti Mälkki · 11 years ago
  2. abe6847 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` by Paul Menzel · 11 years ago
  3. 1cc3416 Add support to enable/disable builtin GbE (again) by Stefan Reinauer · 11 years ago
  4. 714212a Revert "Add support to enable/disable builtin GbE" by Kyösti Mälkki · 11 years ago
  5. eac00d2 intel/sandybridge: Locate CBMEM TOC early in ramstage by Kyösti Mälkki · 11 years ago
  6. d358a50 Add support to enable/disable builtin GbE by Stefan Reinauer · 11 years ago
  7. 483ff82 sandybridge: Store MRC cache in CBFS by Patrick Georgi · 11 years ago
  8. a296ce7 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture by Ronald G. Minnich · 11 years ago
  9. 5750fdd Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h` by Ronald G. Minnich · 11 years ago
  10. 51837f9 Intel Sandy Bridge: udelay.c: Change comparison from <= to < by Paul Menzel · 11 years ago
  11. 243aa44 boot: remove cbmem_post_handling() by Aaron Durbin · 11 years ago
  12. c6f2722 sandybridge: enable ROM caching by Aaron Durbin · 11 years ago
  13. f567f16 sandybridge: add option to mark graphics memory write-combining. by Aaron Durbin · 11 years ago
  14. bb4e79a x86: add new mtrr implementation by Aaron Durbin · 11 years ago
  15. c965076 resources: introduce reserved_ram_resource() by Aaron Durbin · 11 years ago
  16. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  17. 69efaa0 Google Link: Add remaining code to support native graphics by Ronald G. Minnich · 11 years ago
  18. e7ae96f Add Intel Panther Point USB3 initialization by Marc Jones · 12 years ago
  19. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  20. fd611f9 Drop CONFIG_WRITE_HIGH_TABLES by Stefan Reinauer · 11 years ago
  21. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 12 years ago
  22. 4aff445 sconfig: rename pci_domain -> domain by Stefan Reinauer · 12 years ago
  23. 600784e spi.h: Rename the spi.h to spi-generic.h by Zheng Bao · 12 years ago
  24. 6fe0cab Extend CBFS to support arbitrary ROM source media. by Hung-Te Lin · 12 years ago
  25. 816e9d1 Support for Celeron 1007U by Stefan Reinauer · 12 years ago
  26. 5079a0d Remove assembly coded log2 function by Ronald G. Minnich · 12 years ago
  27. e135ac5 Remove AMD special case for LAPIC based udelay() by Patrick Georgi · 12 years ago
  28. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  29. 6446626 Use new system agent binaries by Stefan Reinauer · 12 years ago
  30. 313ec9d Sandybridge: Set PEG clock gating by Marc Jones · 12 years ago
  31. 7e8c8e9 Add PCIe init and NMode flag to PEI data structure by Stefan Reinauer · 12 years ago
  32. e8179b5 Add ddr3lv_support flag to pei_data structure by Duncan Laurie · 12 years ago
  33. 53508fe pei_data.h: Fix comment by Marc Jones · 12 years ago
  34. 48a4a7f Provide MRC with a console printing callback function by Vadim Bendebury · 12 years ago
  35. e5a0a5d Initial IGD OpRegion implementation by Stefan Reinauer · 12 years ago
  36. ad67791 Avoid using hardcoded values in MRC cache code by Vadim Bendebury · 12 years ago
  37. a1ea822 Make coreboot use the offset parameter in cbfstool create by Stefan Reinauer · 12 years ago
  38. 4c8027a Make register/value lists const by Stefan Reinauer · 12 years ago
  39. 357bb2d SandyBridge/IvyBridge: Use flash map to find MRC cache by Stefan Reinauer · 12 years ago
  40. c6b9f92 Add missing newline in error message by Stefan Reinauer · 12 years ago
  41. cf81b82 CMOS: Move MRC seed offset into upper bank by Duncan Laurie · 12 years ago
  42. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  43. 7874e9d Sandybridge: Fix integer overrun in romstage udelay() by Stefan Reinauer · 12 years ago
  44. cf8e466 Cleanup coreboot memory table includes by Kyösti Mälkki · 12 years ago
  45. 9ca1c0a Sandy/Ivy Bridge and Cougar/Panther Point: Fix names by Stefan Reinauer · 12 years ago
  46. 5e29f00 Intel and GFXUMA: drop redundant use of lb_add_memory_range() by Kyösti Mälkki · 12 years ago
  47. 7f189cc Intel Sandybridge and UMA: use mmio_resource() by Kyösti Mälkki · 12 years ago
  48. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  49. d4ee808 sandybridge: reinitialize usbdebug after MRC by Sven Schnelle · 12 years ago
  50. efff733 Refactor driver structs by Patrick Georgi · 12 years ago
  51. 1b3207e CTDP: Only do TDP down/nominal change from TNP0 by Duncan Laurie · 12 years ago
  52. 55864ef ACPI: Add support for runtime config TDP down by Duncan Laurie · 12 years ago
  53. f4d3623 ELOG: Add support for a monotonic boot counter in CMOS by Duncan Laurie · 12 years ago
  54. 696262b More descriptive error messages in Sandybridge raminit code by Stefan Reinauer · 12 years ago
  55. 9c4c6ab ELOG: Fix boot count increment for non-wake case by Duncan Laurie · 12 years ago
  56. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  57. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  58. 6097e19 Make ACPI code detect Sandy/Ivy Bridge dynamically by Stefan Reinauer · 12 years ago
  59. afcaac2 Drop (empty) sandybridge_late_initialization() by Stefan Reinauer · 12 years ago
  60. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  61. 542e962 Print PCI ID of PCH during boot up by Stefan Reinauer · 12 years ago
  62. c664387 Drop leading spaces from CPU name string by Stefan Reinauer · 12 years ago
  63. 4821489 Fix MRC cache update delays by Stefan Reinauer · 12 years ago
  64. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  65. da83a5f Fixes to enable RC6 on IvyBridge by Duncan Laurie · 12 years ago
  66. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  67. 88fc0b9 Sandybridge: Remove remnants of FDT support from MRC cache code by Stefan Reinauer · 12 years ago
  68. 6e901fd Sandybridge: Fix MRC cache calculation by Stefan Reinauer · 12 years ago
  69. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  70. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  71. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  72. f125d80 Add missing newline to printk in Sandybridge init code by Stefan Reinauer · 12 years ago
  73. cafedcf Strip quotes from Sandybridge MRC blob by Stefan Reinauer · 12 years ago
  74. 7a3f36a Sandybridge: Display platform information early by Vadim Bendebury · 12 years ago
  75. 8508cff Update Ivybridge GT power meter tables by Duncan Laurie · 12 years ago
  76. dd585b8 Update ivybridge graphics initialization by Duncan Laurie · 12 years ago
  77. 7b508dd Only send ME Dram Init Done message on Sandybridge by Duncan Laurie · 12 years ago
  78. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  79. e6063fe Fix Sandybridge/Ivybridge mainboards according to code review by Stefan Reinauer · 12 years ago
  80. 6ea86b1 Sandybridge: Temporarily disable MRC cache finding code by Stefan Reinauer · 12 years ago
  81. e9dfdd9 Reverse Vendor ID & Device ID for map_oprom_vendev() by Martin Roth · 12 years ago
  82. 16401b8 SMM: Add udelay on Sandybridge systems by Stefan Reinauer · 12 years ago
  83. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago