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review.coreboot.org / coreboot / b9fe01c881c40ea185a54b13c4ed0d604e6d36f0 / src / southbridge
  1. 5a91692 Set SB800 ROM decode size based on kconfig. by Marc Jones · 13 years ago
  2. 23b2152 Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and by Rudolf Marek · 13 years ago
  3. 811787a i82801gx: read RTC status register to prevent IRQ storm by Sven Schnelle · 13 years ago
  4. 3e706b6 amd southbirdge sb800 wrapper, pci bridge fix by Kerry She · 13 years ago
  5. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  6. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago
  7. d1cb0ee sb800: move spi prefetch and fast read mode to sb bootblock. by Stefan Reinauer · 13 years ago
  8. 8fed77a ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic by Scott Duplichan · 13 years ago
  9. bfe8e51 SMM: don't overwrite SMM memory on resume by Sven Schnelle · 13 years ago
  10. d8c68a9 i82801gx: replace cafed00d/cafebabe by defines by Sven Schnelle · 13 years ago
  11. fed129b Add ACPI automatic PIC/APIC interrupt routing logic for ck804 by Jonathan A. Kollasch · 13 years ago
  12. 486e032 Revert changes to set the sb800 to AHCI mode. by Marc Jones · 13 years ago
  13. e261807 i82801gx: enable ACPI during S3 resume by Sven Schnelle · 13 years ago
  14. f4dc1a7 SMM: add defines for APM_CNT register by Sven Schnelle · 13 years ago
  15. 44c1d31 re-indent, so files conform to coding guidelines. by Stefan Reinauer · 13 years ago
  16. c21b054 SMM: add mainboard_apm_cnt() callback by Sven Schnelle · 13 years ago
  17. e1898b5 vt8237r: Simplify bootblock init to work around nested if() romcc problem by Peter Stuge · 13 years ago
  18. 76d53b2 trivial remove blanks at the end of line by Kerry She · 13 years ago
  19. 991f880 This patch fix a AMD sb800 wrapper compile warning: by Kerry She · 13 years ago
  20. 4053e14 Correct implementation of r6608. (.align actually takes its argument in bytes) by Jonathan Kollasch · 13 years ago
  21. 6409a22 Ensure ck804 romstrap is 16-byte aligned. by Jonathan Kollasch · 13 years ago
  22. 3f0075b cimx_wrapper/sb800: Fix indent in late.c:sb800_enable() by Peter Stuge · 13 years ago
  23. a64ab46 Update gpp port configuration. by Scott Duplichan · 13 years ago
  24. be8fae1 Program the I/O APIC ID. by Scott Duplichan · 13 years ago
  25. f191c72 Enable AHCI mode and hide IDE controller to reduce boot time. by Scott Duplichan · 13 years ago
  26. e78ae24 Configure CIMx to use 33 MHz fast mode for SPD read. by Scott Duplichan · 13 years ago
  27. faafd14 by Kerry She · 13 years ago
  28. eb995c2 by Kerry She · 13 years ago
  29. 49ae971 i82801gx: enable SPI prefetching by Sven Schnelle · 13 years ago
  30. 3e4fb9d more ifdef -> if fixes. by Stefan Reinauer · 13 years ago
  31. d4814bd more ifdef -> if fixes by Stefan Reinauer · 13 years ago
  32. 1d888a9 some ifdef --> if fixes by Stefan Reinauer · 13 years ago
  33. 305f2f5 drop dead code from sb800 bootblock by Stefan Reinauer · 13 years ago
  34. 81725b2e pci1x2x: remove latency/bridge control/cacheline size settings by Sven Schnelle · 13 years ago
  35. 5c72a87 pci1x2x: use cardbus_read_resources()/cardbus_enable_resources() by Sven Schnelle · 13 years ago
  36. 5f22f303 pci1x2x: use pci_ops set_subsystem instead of custom code by Sven Schnelle · 13 years ago
  37. 20f7f3b pci1x2x: add PCI1510 device IDs by Sven Schnelle · 13 years ago
  38. baec034 pci1x2x: use devicetree register configuration by Sven Schnelle · 13 years ago
  39. b297b49 drop dead uart init code. by Stefan Reinauer · 13 years ago
  40. 4c50cb2 Fix compilation of all i82371eb boards when ACPI tables aren't generated by Idwer Vollering · 13 years ago
  41. 582748f Fix some more misuses of ifdef/if defined by Stefan Reinauer · 13 years ago
  42. b3ae186 * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value by Stefan Reinauer · 13 years ago
  43. 8902502 drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH by Stefan Reinauer · 13 years ago
  44. 6108958 nvidia mcp55: drop unused dbg_info by Stefan Reinauer · 13 years ago
  45. 28cd291 cosmetic cleanup of sis966 usb2 code by Stefan Reinauer · 13 years ago
  46. 484281b by Marc Jones · 13 years ago
  47. 5005bb06 Unify use of post_code by Alexandru Gagniuc · 13 years ago
  48. 61aee5f In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__. by Stefan Reinauer · 13 years ago
  49. 8a539b6 ICH7: Fix register naming error by Sven Schnelle · 13 years ago
  50. d3de3ee Add the SR5650 & SP5100 to the Kconfig and Makefile.inc by Zheng Bao · 13 years ago
  51. c342223 SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx. by Zheng Bao · 13 years ago
  52. 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago
  53. ea1c0a7 Fix power_on_after_fail handling on AMD SB600 by Josef Kellermann · 13 years ago
  54. fadb004 Improve ck804 IOAPIC and HPET resource handling. by Jonathan Kollasch · 13 years ago
  55. 7b9bbee Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3. by Alexandru Gagniuc · 13 years ago
  56. 9132102 Use subsystem id from devicetree.cb instead of Kconfig and move by Sven Schnelle · 13 years ago
  57. d175f44 add functions to set Subsystem Vendor/Device to rl5c746 by Sven Schnelle · 13 years ago
  58. 199c694 It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. by Rudolf Marek · 13 years ago
  59. 855224b Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600 by Josef Kellermann · 13 years ago
  60. 650cf23 Fix build errors introduced in r6367 by Alexandru Gagniuc · 13 years ago
  61. 025ead7 Extended K8T890 driver to include the K8T800 and K8M800 northbridges by Alexandru Gagniuc · 13 years ago
  62. dd6c1e6 SERIAL_POST was renamed to CONSOLE_POST a while ago by Stefan Reinauer · 13 years ago
  63. cf37a59 Removed LPC DMA Deadlock workaround... by Josef Kellermann · 13 years ago
  64. 63e62b0 This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code. by Frank Vibrans · 13 years ago
  65. 74ad66c Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC. by Rudolf Marek · 13 years ago
  66. 20ecc5a RS690: Provide support for MMCONF. by Josef Kellermannseppk · 13 years ago
  67. a96b218 Fix subvendor/subdevice programming on RS690 by Josef Kellermann · 13 years ago
  68. 87fcffa Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions by Patrick Georgi · 13 years ago
  69. 5c0bca2 Inverse two arguments of cbfs-files-y and adapts its users (one of which already used the new order) by Patrick Georgi · 13 years ago
  70. 86bd99a by Rudolf Marek · 13 years ago
  71. 1c2734f Fix Bimini build by Stefan Reinauer · 13 years ago
  72. a5c949e Trivial. Re-indent the code. by Zheng Bao · 13 years ago
  73. 066cbe0 Set the phy via weak function. As Rudolf called. by Zheng Bao · 13 years ago
  74. 9dcca3b Set the SB800 SATA PHY correctly. by Zheng Bao · 13 years ago
  75. a302b58 Change fadt revision back to 3. by Zheng Bao · 13 years ago
  76. 72cc87f Now bimini can boot linux to login. by Zheng Bao · 13 years ago
  77. a4da254 S3 feanture of SB800. Compiliant with SB700. by Zheng Bao · 13 years ago
  78. 79c04d5 Move some board specific functions to sb800.h. by Zheng Bao · 13 years ago
  79. d098575 This sb800 code is derived from sb700. by Zheng Bao · 13 years ago
  80. a19c622 remove the code which is not ready to release. by Zheng Bao · 13 years ago
  81. 752ab0d remove the code which is not ready to release. by Zheng Bao · 13 years ago
  82. fb433be drop unused files by Stefan Reinauer · 14 years ago
  83. 09e0e9a change a readable way to fix SB800 CIMX "multi-character constant warning". by Kerry She · 14 years ago
  84. c7f0c8f MCP55: Cosmetic fixes, switch to u8 et al. by Uwe Hermann · 14 years ago
  85. 7e2fbd5 CK804: Cosmetic fixes, switch to u8 et al. by Uwe Hermann · 14 years ago
  86. e925965 src/southbridge/amd/cimx_wrapper: Run dos2unix on the files. by Uwe Hermann · 14 years ago
  87. d6a1373 AMD SB800: Drop component prefix from filenames. by Uwe Hermann · 14 years ago
  88. 84f59ae Add AMD SB800 southbridge support via cimx_wrapper. by Kerry She · 14 years ago
  89. 40992d3 Add RS785(RS880) support. Just few pci_ids. by Zheng Bao · 14 years ago
  90. 8098e42 Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code by Nils Jacobs · 14 years ago
  91. 84be0f5 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) by Nils Jacobs · 14 years ago
  92. ef15ff4 -Clean up some comments. by Nils Jacobs · 14 years ago
  93. acda2fc Intel SCH: make state machine binary selection available in Kconfig for now. by Stefan Reinauer · 14 years ago
  94. 2d1d9ceb Random fixes for TI pci1x2x / Nokia IP530 / others. by Uwe Hermann · 14 years ago
  95. 2c36627 SMM on AMD K8 Part 2/2 by Rudolf Marek · 14 years ago
  96. cadc545 SMM for AMD K8 Part 1/2 by Stefan Reinauer · 14 years ago
  97. 405721d Fix a few whitespace and coding style issues. by Uwe Hermann · 14 years ago
  98. a0360af A couple of Poulsbo fixes: by Patrick Georgi · 14 years ago
  99. be61a17 Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board which uses it. by Patrick Georgi · 14 years ago
  100. b9c224e Add TINY_BOOTBLOCK support for the SiS966 southbridge. by Uwe Hermann · 14 years ago