pci1x2x: remove latency/bridge control/cacheline size settings

Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
3 files changed
tree: 36d93d3eaa95598bef4c64e6595aa454993cfa5e
  1. documentation/
  2. payloads/
  3. src/
  4. util/
  5. COPYING
  6. Makefile
  7. Makefile.inc
  8. README