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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / soc / imgtec / pistachio / ddr2_init.c
  1. 721f299 imgtec/pistachio: DDR2, DDR3: DLL reset set by Ionela Voinescu · 9 years ago
  2. 6b95406 imgtec/pistachio: DDR2, DDR3: DQS gate early by Ionela Voinescu · 9 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. 3fa1ad0 pistachio: add DDR3 initialization code by Ionela Voinescu · 9 years ago
  5. 1185c10 pistachio: Use passive windowing as DQS gating scheme by Ionela Voinescu · 9 years ago
  6. 1d4c305 pistachio: sort included header files by Ionela Voinescu · 9 years ago
  7. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  8. 5d997f9 imgtec/pistachio: DDR reads return to controller with no bubbles by Ionela Voinescu · 9 years ago
  9. a2c4f9e imgtec/pistachio: DDR row/bank/column mapping by Ionela Voinescu · 9 years ago
  10. 823f607 pistachio: Remove 50% DDR bandwidth restriction by Ionela Voinescu · 9 years ago
  11. 51ad6ac pistachio: Decrease DDR ODT from 75R to 50R by Ionela Voinescu · 9 years ago
  12. 59074ff pistachio: clean DDR2 initialization code by Ionela Voinescu · 9 years ago
  13. d6aaca9 pistachio: add DDR2 initialization code by Ionela Voinescu · 9 years ago