Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
91d1e76fd168defce4132d1e308b68a2013a89df
/
src
/
include
/
cpu
« Previous
98dda06
cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__
by Vladimir Serbinenko
· 11 years ago
88a67f0
AMD boards (non-AGESA): Cleanup earlymtrr.c includes
by Kyösti Mälkki
· 11 years ago
911cedf
lynxpoint: Route all USB ports to XHCI in finalize step
by Duncan Laurie
· 11 years ago
66e0c4c
cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
by Alexandru Gagniuc
· 11 years ago
f0a13ce
AMD boards: Fix includes for microcode updates
by Kyösti Mälkki
· 11 years ago
0edc224
smi: Update mainboard_smi_gpi() to have 32bit argument
by Duncan Laurie
· 11 years ago
fd4f413
Rename cpu/x86/car.h to arch/early_variables.h
by Stefan Reinauer
· 11 years ago
cbf5bdf
CBMEM: Always select CAR_MIGRATION
by Kyösti Mälkki
· 11 years ago
c66f1cb
Include boot_cpu.c for romstage builds
by Kyösti Mälkki
· 11 years ago
5d7d09c
AMD Kabini: Add CPU AGESA wrapper for new AMD processor family
by Siyuan Wang
· 11 years ago
0cb07e3
include: Fix spelling
by Martin Roth
· 11 years ago
8048e74
include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines
by Paul Menzel
· 11 years ago
5750fdd
Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
by Ronald G. Minnich
· 11 years ago
716738a
x86: add cache-as-ram migration option
by Aaron Durbin
· 11 years ago
33cde9a
Make early x86 POST codes written to IO port optional
by Martin Roth
· 11 years ago
c5e036a
Get rid of a number of __GNUC__ checks
by Stefan Reinauer
· 11 years ago
3f5f6d8
Drop prototype guarding for romcc
by Stefan Reinauer
· 11 years ago
758076c
x86: use asmlinkage macro for smm_handler_t
by Aaron Durbin
· 11 years ago
8e73b5d
x86: add TSC_CONSTANT_RATE option
by Aaron Durbin
· 11 years ago
bebf669
x86: use boot state callbacks to disable rom cache
by Aaron Durbin
· 11 years ago
8ecec21
Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"
by Nico Huber
· 11 years ago
1fde22c
siemens/sitemp_g1p1: Make ACPI report the right mmconf region
by Patrick Georgi
· 11 years ago
6ccb1ab
mtrr: add rom caching comment about hyperthreads
by Aaron Durbin
· 11 years ago
190011e
AMD: Drop six copies of wrmsr_amd and rdmsr_amd
by Kyösti Mälkki
· 11 years ago
d46161e
intel/microcode.h: Fix typo in comment: micr*o*code
by Paul Menzel
· 11 years ago
ebf142a
boot: add disable_cache_rom() function
by Aaron Durbin
· 11 years ago
bc07f5d
x86: add rom cache variable MTRR index to tables
by Aaron Durbin
· 11 years ago
77a5b40
x86: mtrr: add CONFIG_CACHE_ROM support
by Aaron Durbin
· 11 years ago
bb4e79a
x86: add new mtrr implementation
by Aaron Durbin
· 11 years ago
57686f8
x86: unify amd and non-amd MTRR routines
by Aaron Durbin
· 11 years ago
24d1d4b
x86: Unify arch/io.h and arch/romcc_io.h
by Stefan Reinauer
· 11 years ago
ef4275b
x86: protect against abi assumptions from compiler
by Aaron Durbin
· 12 years ago
98ffb42
intel microcode: split up microcode loading stages
by Aaron Durbin
· 12 years ago
69efaa0
Google Link: Add remaining code to support native graphics
by Ronald G. Minnich
· 12 years ago
1fef1f5
haswell: reserve default SMRAM space
by Aaron Durbin
· 12 years ago
50a3464
x86: SMM Module Support
by Aaron Durbin
· 12 years ago
a46a712
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
by Paul Menzel
· 12 years ago
62f100b
smm: Update rev 0x30101 SMM revision save state
by Aaron Durbin
· 12 years ago
92f03c0
AMD Family12h: Fix warnings
by Martin Roth
· 12 years ago
8cc8468
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
by Patrick Georgi
· 12 years ago
644e83b
speedstep: Deduplicate some MSR identifiers
by Patrick Georgi
· 12 years ago
399486e
Unify assembler function handling
by Stefan Reinauer
· 12 years ago
8ada152
Unify use of bool config variables
by Stefan Reinauer
· 12 years ago
7f3d442
SMM: Avoid use of global variables in SMI handler
by Duncan Laurie
· 12 years ago
8b93059
Pass the CPU index as a parameter to startup.
by Ronald G. Minnich
· 12 years ago
a571c70
Fix gcc-4.7 building problem.
by Han Shen
· 12 years ago
a74af56
Overhaul speedstep code
by Nico Huber
· 12 years ago
41392df
Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
by Nico Huber
· 12 years ago
00b579a
buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc
· 12 years ago
dbc4739
AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution
by Kyösti Mälkki
· 12 years ago
0db6820
Synchronize rdtsc instructions
by Stefan Reinauer
· 12 years ago
7bdf85b
Move cpus_ready_for_init() to AMD K8
by Kyösti Mälkki
· 12 years ago
51676b1
Revert "Use broadcast SIPI to startup siblings"
by Sven Schnelle
· 12 years ago
ace7a6a
SMM: rename tseg_fixup to tseg_relocate and export
by Duncan Laurie
· 12 years ago
51cb26d
SMM: Fix state save map for sandybridge and TSEG
by Duncan Laurie
· 12 years ago
537b4e0
Add code to read Intel microcode from CBFS
by Vadim Bendebury
· 12 years ago
5458b9d
Intel cpus: Extend cache to cover complete Flash Device
by Kyösti Mälkki
· 12 years ago
2c08f6a
AGESA F15 wrapper for Trinity
by zbao
· 12 years ago
042c146
Use broadcast SIPI to startup siblings
by Sven Schnelle
· 12 years ago
9ed1456
Intel CPUs: execute microcode update only once per core
by Kyösti Mälkki
· 12 years ago
2f00ce3
cbtypes.h: Unify cbtypes.h used in AMD board's code
by Vikram Narayanan
· 12 years ago
e166782
Clean up #ifs
by Patrick Georgi
· 12 years ago
bf34e94
SMM: unify mainboard APM command handlers
by Stefan Reinauer
· 12 years ago
ac8209a
cpu/cpu.h: add ROMCC guards
by Stefan Reinauer
· 12 years ago
3f8989e
Revamp Intel microcode update code
by Stefan Reinauer
· 12 years ago
05e740f
Replace cache control magic numbers with symbols
by Patrick Georgi
· 12 years ago
2bdfb48
Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer
· 12 years ago
3aa067f
Add support to run SMM handler in TSEG instead of ASEG
by Stefan Reinauer
· 12 years ago
ea37a21
Add support for Intel Turbo Boost feature
by Stefan Reinauer
· 12 years ago
7b67892
Make MTRR min hole alignment 64MB
by Duncan Laurie
· 13 years ago
00093a8
Add an option to keep the ROM cached after romstage
by Stefan Reinauer
· 13 years ago
19e7e7d
Add infrastructure for global data in the CAR phase of boot
by Gabe Black
· 13 years ago
1a34165
xchg is atomic with side-effects
by Patrick Georgi
· 12 years ago
c8feedd
Unify Local APIC address definitions
by Patrick Georgi
· 13 years ago
d3e990c
AGESA F15: AGESA family15 model 00-0fh cpu wrapper
by Kerry Sheh
· 13 years ago
adfbcb79
MTRR: get physical address size from CPUID
by Sven Schnelle
· 13 years ago
5ff7c13
remove trailing whitespace
by Stefan Reinauer
· 13 years ago
784544b
Remove XIP_ROM_BASE
by Patrick Georgi
· 13 years ago
1da1046
Get rid of AUTO_XIP_ROM_BASE
by Patrick Georgi
· 13 years ago
83d59b9
Build warning fix for AMD Family 12
by efdesign98
· 13 years ago
78834b7
Miscellaneous AMD F14 warning fixes
by efdesign98
· 13 years ago
1ac19e2
cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
by Keith Hui
· 13 years ago
b5b3b3b
Make AMD SMM SMP aware
by Rudolf Marek
· 13 years ago
7c0c64e
Addition of Family12/SB900 wrapper code
by efdesign98
· 13 years ago
180f81e
SMM: add guard and include types.h in cpu/x86/smm.h
by Sven Schnelle
· 13 years ago
bfe8e51
SMM: don't overwrite SMM memory on resume
by Sven Schnelle
· 13 years ago
f4dc1a7
SMM: add defines for APM_CNT register
by Sven Schnelle
· 13 years ago
c21b054
SMM: add mainboard_apm_cnt() callback
by Sven Schnelle
· 13 years ago
8c46263
Cosmetic cleanup.
by Scott Duplichan
· 13 years ago
d4814bd
more ifdef -> if fixes
by Stefan Reinauer
· 13 years ago
1d888a9
some ifdef --> if fixes
by Stefan Reinauer
· 13 years ago
5005bb06
Unify use of post_code
by Alexandru Gagniuc
· 13 years ago
61aee5f
In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.
by Stefan Reinauer
· 13 years ago
6b4674e
I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.
by Frank Vibrans
· 14 years ago
7b0500c
Revert r5902 to make code more readable again. At least three people like to
by Stefan Reinauer
· 14 years ago
5bb9fd6
Now that the VIA code is run above 1Meg (like other boards), it should
by Kevin O'Connor
· 14 years ago
84be0f5
-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
by Nils Jacobs
· 14 years ago
3344743
Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
by Nils Jacobs
· 14 years ago
1c6d4e6
Clean up Geode GX2 comments, whitespace and coding style. Trivial.
by Nils Jacobs
· 14 years ago
cadc545
SMM for AMD K8 Part 1/2
by Stefan Reinauer
· 14 years ago
Next »