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review.coreboot.org / coreboot / 77133afe3142096cc7ea7755bfc727f59f2282f9 / src / southbridge / amd / sr5650 / pcie.c
  1. 72c83a8 sb/amd/sr5650: Allow resource allocator to assign bus numbers by Timothy Pearson · 9 years ago
  2. a8c6c7f southbridge/amd/sr5650: Hide clock configuration device after setup is complete by Timothy Pearson · 9 years ago
  3. 21be0d2 src/southbridge/amd/sr5650: Always configure lane director on startup by Timothy Pearson · 9 years ago
  4. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  5. 535452d southbridge/amd/sr5650: Fix hardcoded printk() function names in pcie.c by Timothy Pearson · 9 years ago
  6. c3fcdcc southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16 by Timothy Pearson · 9 years ago
  7. 4cde978 southbridge/amd/sr5650: Fix GPP3a link training in higher width modes by Timothy Pearson · 9 years ago
  8. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  9. 55e31a9 southbridge/amd amd81XX, cs553X & sr5650 spelling fixes by Martin Roth · 10 years ago
  10. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  11. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  12. af3dce9 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c. by Stefan Reinauer · 13 years ago
  13. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  14. 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago