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review.coreboot.org / coreboot / 77133afe3142096cc7ea7755bfc727f59f2282f9 / src / southbridge / amd / sr5650
  1. 77133af sb/amd/sr5650: Correctly locate CPU MMCONFIG resource by Timothy Pearson · 9 years ago
  2. 1eaaa0e southbridge/amd/sr5650: Add MCFG ACPI table support by Timothy Pearson · 9 years ago
  3. 16ff807 amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes by Timothy Pearson · 9 years ago
  4. 72c83a8 sb/amd/sr5650: Allow resource allocator to assign bus numbers by Timothy Pearson · 9 years ago
  5. 56c8ef9 southbridge/amd/sr5650: Use correct PCI configuration block offset by Timothy Pearson · 9 years ago
  6. a8c6c7f southbridge/amd/sr5650: Hide clock configuration device after setup is complete by Timothy Pearson · 9 years ago
  7. 44e4a4e southbridge/amd/sr5650: Add IOMMU support by Timothy Pearson · 9 years ago
  8. 21be0d2 src/southbridge/amd/sr5650: Always configure lane director on startup by Timothy Pearson · 9 years ago
  9. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  10. 7a5413a southbridge/amd/sr5650: Add AMD Family 15h CPU support by Timothy Pearson · 9 years ago
  11. 535452d southbridge/amd/sr5650: Fix hardcoded printk() function names in pcie.c by Timothy Pearson · 9 years ago
  12. c3fcdcc southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16 by Timothy Pearson · 9 years ago
  13. 5a0efd2 southbridge/amd/sr5650: Add optional delay after link training by Timothy Pearson · 9 years ago
  14. 4cde978 southbridge/amd/sr5650: Fix GPP3a link training in higher width modes by Timothy Pearson · 9 years ago
  15. cbda504 southbridge/amd/sr5650: Remove unnecessary register configuration by Timothy Pearson · 9 years ago
  16. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  17. 13e4182 kbuild: automatically include southbridges by Stefan Reinauer · 9 years ago
  18. bde6d30 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer by Kevin Paul Herbert · 10 years ago
  19. 55e31a9 southbridge/amd amd81XX, cs553X & sr5650 spelling fixes by Martin Roth · 10 years ago
  20. a9a2e10 southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop by Edward O'Callaghan · 10 years ago
  21. 0f92f63 Uniformly spell frequency unit symbol as Hz by Elyes HAOUAS · 10 years ago
  22. 6a12109 AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment by Paul Menzel · 11 years ago
  23. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  24. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  25. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  26. 8ada152 Unify use of bool config variables by Stefan Reinauer · 12 years ago
  27. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  28. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  29. da52aed Fixes Fam10/SR5650 cpu not recognized message. by Dave Frodin · 12 years ago
  30. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  31. af3dce9 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c. by Stefan Reinauer · 13 years ago
  32. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  33. 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago