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review.coreboot.org / coreboot / 77133afe3142096cc7ea7755bfc727f59f2282f9 / src / soc / imgtec / pistachio / include / soc
  1. 4f3d400 imgtec/pistachio: disable default RPU gate register values by Ionela Voinescu · 9 years ago
  2. 3218e79 imgtec/pistachio: memlayout: update GRAM size by Ionela Voinescu · 9 years ago
  3. 7100cf2 imgtec/pistachio: Add SOC_REGISTERS memory region by Ionela Voinescu · 9 years ago
  4. 90d1235 mainboard/google/urara: change SYS PLL to 700MHz by Ionela Voinescu · 9 years ago
  5. 6b95406 imgtec/pistachio: DDR2, DDR3: DQS gate early by Ionela Voinescu · 9 years ago
  6. f6d3bd4 imgtec/pistachio: increase CBFS cache by Ionela Voinescu · 9 years ago
  7. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  8. e5bad5c verstage: use common program.ld for linking by Aaron Durbin · 9 years ago
  9. 6123490 imgtech/pistacho: Add vboot2 memory region by Patrick Georgi · 9 years ago
  10. 3fa1ad0 pistachio: add DDR3 initialization code by Ionela Voinescu · 9 years ago
  11. 1d4c305 pistachio: sort included header files by Ionela Voinescu · 9 years ago
  12. 4f2f01a pistachio: increase romstage size by Ionela Voinescu · 9 years ago
  13. f4e859b Revert "pistashio: bump up romstage size" by Aaron Durbin · 9 years ago
  14. def0fb5 pistashio: bump up romstage size by Aaron Durbin · 9 years ago
  15. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  16. b4a6ca9 imgtec/pistachio: Add comment on the unusual memory layout by Patrick Georgi · 9 years ago
  17. 6e944c4 imgtech/pistachio: Give some more space to the bootblock by Patrick Georgi · 9 years ago
  18. 11ecdb7 imgtec/pistachio: increase RAM CBFS cache size by Vadim Bendebury · 9 years ago
  19. 38063b0 pistachio: add clock setup for all I2C interfaces by Ionela Voinescu · 9 years ago
  20. b8936ad urara: Identity map DRAM/SRAM by Andrew Bresticker · 10 years ago
  21. d6aaca9 pistachio: add DDR2 initialization code by Ionela Voinescu · 10 years ago
  22. fdce680 pistachio: implement clock setup for I2C0 by Ionela Voinescu · 10 years ago
  23. 8b1f23e urara: add clock setup for MIPS CPU, ROM and Ethernet by Ionela Voinescu · 10 years ago
  24. 30fc667 pistachio: increase size of bootblock to 18 KB by Ionela Voinescu · 10 years ago
  25. 55b8dc0 pistachio: change memory layout as to allow bigger CBFS cache by Ionela Voinescu · 10 years ago
  26. b3f666b urara: Configure clocks and MFIOs by Ionela Voinescu · 10 years ago
  27. b9d9615 urara: add support for DMA coherent memory area by Ionela Voinescu · 10 years ago
  28. fb3ea74 pistachio: increase the size of romstage to 36K by Ionela Voinescu · 10 years ago
  29. 420b0f6 pistachio: add timer frequency for SOC; correct platform ID by Ionela Voinescu · 10 years ago
  30. fe51cc4 pistachio: modify memory layout by Vadim Bendebury · 10 years ago
  31. 52a8879 pistachio: implement timer support by Vadim Bendebury · 10 years ago
  32. 0812568 pistachio: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  33. 1d84ef5 pistachio: add gpio type definition by Vadim Bendebury · 10 years ago