Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
66b0d55d326540e400ad3fa5130666dbd03b9694
/
src
/
soc
/
intel
/
skylake
/
romstage
b7fa7fb
soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB
by Barnali Sarkar
· 8 years ago
e65affa
soc/intel/skylake: add PrmrrSize to chip config
by Robbie Zhang
· 8 years ago
d8e34b2
driver/intel/fsp1_1: Fix boot failure for non-verstage case
by Teo Boon Tiong
· 8 years ago
15b7163
soc/intel/skylake: Rename car_stage.S for fsp2_0
by Teo Boon Tiong
· 8 years ago
42cfdf5
soc/intel/skylake: Use the new SPI driver interface
by Furquan Shaikh
· 8 years ago
ffc934d
intel MMA: Enable MMA with FSP2.0
by Pratik Prajapati
· 8 years ago
847da79
soc/intel/skylake: Remove redundant BootLoaderTolumSize assignment
by Subrata Banik
· 8 years ago
79239b7
soc/intel/skylake: Pass proper CPU flex ratio override to FSP
by Naresh G Solanki
· 8 years ago
f796c6e
driver/intel/fsp2_0: Add version parameter to FSP platform callback
by Andrey Petrov
· 8 years ago
c28984d
spi: Clean up SPI flash driver interface
by Furquan Shaikh
· 8 years ago
5bf42c6
soc/intel/skylake: Add FSP 2.0 support in romstage
by Barnali Sarkar
· 8 years ago
1222a73
skylake: Add initial FSP2.0 support
by Rizwan Qureshi
· 8 years ago
3ad6356
soc/intel/skylake: Correct Cache as ram size
by Rizwan Qureshi
· 8 years ago
ecd9a94
soc/intel/skylake: Move bootblock specific code from skylake/romstage
by Naresh G Solanki
· 8 years ago
cf73c13
skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
by Rizwan Qureshi
· 8 years ago
0bb6229
soc/intel/skylake: restore MCHBAR and DMIBAR programming
by Rizwan Qureshi
· 8 years ago
49eca13
soc/intel/skylake: Change name pmc_tco_regs to smbus_tco_regs
by Barnali Sarkar
· 8 years ago
0dddcd7
soc/intel/skylake: Cleanup patch for Skylake SoC
by Barnali Sarkar
· 8 years ago
5d41949
soc/intel/skylake: Add Kabylake device Ids
by Rizwan Qureshi
· 8 years ago
90ed31b
intel/skylake: Enable signalling of error condition
by Patrick Georgi
· 8 years ago
e4a8537
soc/intel/skylake: Add C entry bootblock support
by Subrata Banik
· 8 years ago
0325dc6
bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
by Furquan Shaikh
· 8 years ago
2a12e2e
vboot: Separate vboot from chromeos
by Furquan Shaikh
· 8 years ago
e0a4914
soc/intel/skylake: use common Intel ACPI hardware definitions
by Aaron Durbin
· 8 years ago
222381e
skylake: Generate ACPI timing values for I2C devices
by Duncan Laurie
· 8 years ago
4001f24
skylake: Support common LPSS I2C driver
by Duncan Laurie
· 8 years ago
efcddd9
skylake: Increase IGD stolen size to 64MB
by Duncan Laurie
· 9 years ago
5f0cd58
skylake: Check for power failure when WAK_STS is not set
by Duncan Laurie
· 9 years ago
cbc3c37
intel/skylake: implement vboot_platform_prepare_reboot()
by Aaron Durbin
· 9 years ago
a1faa4c
intel/skylake: implement vboot_platform_is_resuming()
by Aaron Durbin
· 9 years ago
fbdc719
intel/skylake: Implement native Cache-as-RAM (CAR)
by Subrata Banik
· 9 years ago
5535cea
intel/skylake: Disable SaGv in recovery mode
by haridhar
· 9 years ago
ddd9f1a
intel/skylake: Add devicetree setting for DDR frequency limit UPD
by Duncan Laurie
· 9 years ago
b57772d
intel/skylake: Update UPD parameters as per FSP 1.8.0
by Barnali Sarkar
· 9 years ago
a73b931
tree: drop last paragraph of GPL copyright header
by Patrick Georgi
· 9 years ago
66208bd
FSP 1.1: Replace soc_ prefix with fsp_
by Lee Leahy
· 9 years ago
952cb03
intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update
by Rizwan Qureshi
· 9 years ago
b66d673
skylake: add support for verstage
by Aaron Durbin
· 9 years ago
e6af4be
intel fsp1_1: prepare for romstage vboot verification split
by Aaron Durbin
· 9 years ago
cc5ac17
soc/intel/common: remove chipset specific calls
by Aaron Durbin
· 9 years ago
3c4053f
intel SOC common: Remove unused parameters
by Lee Leahy
· 9 years ago
a400327
chromeos: vboot and chromeos dependency removal for sw write protect state
by Paul Kocialkowski
· 9 years ago
9ae6cd4
Skylake:Set DISB inside romstage after mrc init
by Dhaval Sharma
· 9 years ago
15c220d
skylake: Remove dead code
by Lee Leahy
· 9 years ago
ce03aaf
skylake: move flash_controller.h to the proper place
by Aaron Durbin
· 9 years ago
7a2defb
intel/skylake: Implement HW Sequence based WP status read functionality
by Barnali Sarkar
· 9 years ago
08a6fd3
intel/skylake: Fix RMT disable of saved training data
by Duncan Laurie
· 9 years ago
c07cdfe
intel/skylake: Force full memory train if RMT is enabled
by Duncan Laurie
· 9 years ago
9dcd4f0
fsp raminit: Add romstage_params to soc_memory_init_params
by Duncan Laurie
· 9 years ago
5c1c3d6
skylake: Update Memory and Silicon Init params
by Rizwan Qureshi
· 9 years ago
ccb01f7
skylake: pass IED_REGION_SIZE Kconfig to FSP
by Aaron Durbin
· 9 years ago
ab16b33
skylake: use native gpio configuration for uart
by Aaron Durbin
· 9 years ago
e33a172
skylake: fix serial port with new code base
by Aaron Durbin
· 9 years ago
31be8e4
skylake: Fix building without serial console
by Duncan Laurie
· 9 years ago
76d1671
skylake: add global reset cause registers to power state
by Aaron Durbin
· 9 years ago
e94c40b
skylake: take into account deep s3 in power failure check
by Aaron Durbin
· 9 years ago
a3d36bd
skylake: read out and report full width of gen_pmcon registers
by Aaron Durbin
· 9 years ago
46ca690
intel/skylake: support 32bit uart8250_mem driver in romstage
by Naveen Krishna Chatradhi
· 9 years ago
1b9635d
Skylake: Initialize GPIOs for UART2
by rsatapat
· 9 years ago
5c56ce1
Skylake: Only support UART2 as debug port, clean up the rest
by Naveen Krishna Chatradhi
· 9 years ago
02b3243
skylake: honor pcie root port settings already in chip.h
by Aaron Durbin
· 9 years ago
356cabb
skylake: Show SPI controller if enabled in devicetree.cb
by Duncan Laurie
· 9 years ago
1d14b3e
soc/intel: Add Skylake SOC support
by Lee Leahy
· 9 years ago
b000513
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
by Lee Leahy
· 9 years ago