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review.coreboot.org / coreboot / 43105d6a5a4898386e35c4fdccdf643b95faef98 / src / cpu
  1. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  2. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  3. 3b5a9ed Fix register corruption during Intel Microcode update by Stefan Reinauer · 12 years ago
  4. 252111d Don't include console.h in microcode.c when compiling with ROMCC by Stefan Reinauer · 12 years ago
  5. 2c41c40 Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards by Stefan Reinauer · 12 years ago
  6. a1155b4 Move VSA support from x86 to Geode by Patrick Georgi · 12 years ago
  7. 943ddce Make geode_lx use the vsa from blobs repository by Patrick Georgi · 12 years ago
  8. c31384e Fix up Sandybridge C state generation code by Stefan Reinauer · 12 years ago
  9. 4cc8c70 Rework ACPI CST table generation by Stefan Reinauer · 12 years ago
  10. ae5e11d Move top level pc80 directory to drivers/ by Stefan Reinauer · 12 years ago
  11. 3110945 microcode: print date of microcode and unify output by Stefan Reinauer · 12 years ago
  12. 3f8989e Revamp Intel microcode update code by Stefan Reinauer · 12 years ago
  13. 05e740f Replace cache control magic numbers with symbols by Patrick Georgi · 12 years ago
  14. 1e6bf09 amd: Fix unused variable warning by Vikram Narayanan · 12 years ago
  15. d6e4d51 Revert wbind added to the reset_vector by Marc Jones · 12 years ago
  16. f722373 S3 code in coreboot public folder. by zbao · 12 years ago
  17. 3925622 S3 code in vendorcode folder. by zbao · 12 years ago
  18. 05758bd Remove obsolete empy macro definition by Ron Minnich · 12 years ago
  19. 2bdfb48 Fixes and Sandybridge support for lapic cpu init by Stefan Reinauer · 12 years ago
  20. f8c7c23 Fix support for RAM-less multi-processor init by Kyösti Mälkki · 12 years ago
  21. 334532e Add Sandybridge/Cougar Point support to SMM relocation handler by Stefan Reinauer · 12 years ago
  22. c00dfbc Cache 8MB flash instead of 4MB by Stefan Reinauer · 12 years ago
  23. 5b6404e Fix timer frequency detection on Sandybridge by Stefan Reinauer · 12 years ago
  24. deda997 Invalidate cache before first jump by Stefan Reinauer · 12 years ago
  25. 8c5b58e Update documentation in smmrelocate.S to mention TSEG by Stefan Reinauer · 12 years ago
  26. 5c55463 Add support for Intel Sandybridge CPU by Stefan Reinauer · 12 years ago
  27. 3aa067f Add support to run SMM handler in TSEG instead of ASEG by Stefan Reinauer · 12 years ago
  28. ea37a21 Add support for Intel Turbo Boost feature by Stefan Reinauer · 12 years ago
  29. abdf15f Apply cache-as-ram conditionally on socket mPGA604 by Kyösti Mälkki · 12 years ago
  30. afd141d S3 code whitespaces changes. by zbao · 12 years ago
  31. 819c7d4 Whitespace fixes by Patrick Georgi · 12 years ago
  32. a860c68 Intel cpus: get MAXPHYADDR at runtime for new CAR by Kyösti Mälkki · 12 years ago
  33. 0078ceb Intel cpus: add hyper-threading CPU support to new CAR by Kyösti Mälkki · 12 years ago
  34. 05d6ffb Intel cpus: improve CPU compatibility of new CAR by Kyösti Mälkki · 12 years ago
  35. 7dfe32c Add support for RAM-less multi-processor init by Kyösti Mälkki · 12 years ago
  36. f9d1a42 Intel cpus: apply some good programming practices in new CAR by Kyösti Mälkki · 12 years ago
  37. 325b92f Intel cpus: cache actual size of the Flash ROM device by Kyösti Mälkki · 12 years ago
  38. 5a660ca Intel cpus: copy model_6ex CAR code by Kyösti Mälkki · 12 years ago
  39. 7b67892 Make MTRR min hole alignment 64MB by Duncan Laurie · 13 years ago
  40. 527fc74 Fix MB calculation in the reporting of the MTRR hole by Duncan Laurie · 13 years ago
  41. 7389fa9 MTRR: add alternate allocation method for odd memory maps by Duncan Laurie · 13 years ago
  42. 8bb7723 Add Kconfig options to enable TSEG and set a size by Duncan Laurie · 13 years ago
  43. 67aa3d6 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed by Stefan Reinauer · 13 years ago
  44. 00093a8 Add an option to keep the ROM cached after romstage by Stefan Reinauer · 13 years ago
  45. a01ae62 Fix possible deadlock on SMP stop_this_cpu by Kyösti Mälkki · 12 years ago
  46. 8b28d50 Intel cpus: Fix deadlock on hyper-threading init by Kyösti Mälkki · 12 years ago
  47. 7a39446 Intel cpus: Include CAR from socket by Kyösti Mälkki · 12 years ago
  48. d11ca1d Rename AMD_AGESA to CPU_AMD_AGESA by Kyösti Mälkki · 12 years ago
  49. f5bb477 Fix AMD Agesa leaking Kconfig by Kyösti Mälkki · 12 years ago
  50. 1c93d90 ROMCC boards have no XIP limit by Patrick Georgi · 12 years ago
  51. d4d5e4d Via Epia-N and C3: Set ioapic delivery type in Kconfig by Patrick Georgi · 12 years ago
  52. 7863015 Fix address of IDT in real-mode entry by Kyösti Mälkki · 12 years ago
  53. 8907e81 move console includes to central console/console.h by Stefan Reinauer · 13 years ago
  54. c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
  55. d8d8c63 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. by Marc Jones · 12 years ago
  56. 472efa6 Remove whitespace. by Patrick Georgi · 12 years ago
  57. d3e990c AGESA F15: AGESA family15 model 00-0fh cpu wrapper by Kerry Sheh · 12 years ago
  58. 53c1d20 Intel cpus: use CPU_PHYSMASK_HI define in CAR by Kyösti Mälkki · 12 years ago
  59. adf105f Intel model_106cx: Use symbolic names for MTRR bits by Kyösti Mälkki · 12 years ago
  60. 7916f4c AMD Geode cpus: apply un-written naming rules by Kyösti Mälkki · 12 years ago
  61. e13632a Intel cpus: apply un-written naming rules by Kyösti Mälkki · 12 years ago
  62. 6d64ade Add Intel Socket LGA771 by Sven Schnelle · 13 years ago
  63. 12b7262 VIA cpus: apply un-written naming rules by Kyösti Mälkki · 12 years ago
  64. 0713ca3 post code: Replaced hard-coded post code with macro by Vikram Narayanan · 13 years ago
  65. 15370ca trivial: spelling fixes in comments by Vikram Narayanan · 13 years ago
  66. c6daaa7 Leave SSE and MMX instructions enabled in coreboot by Stefan Reinauer · 13 years ago
  67. adfbcb79 MTRR: get physical address size from CPUID by Sven Schnelle · 13 years ago
  68. eb84f6a Fix Geode GX2 + LX caching for tiny bootblock. by Nils Jacobs · 13 years ago
  69. 8d84613 ACPI: mark empty get_cst_entries() weak by Sven Schnelle · 13 years ago
  70. 79cfe7e Fix Fam10 MMCONF_SUPPORT_DEFAULT setting. by Marc Jones · 13 years ago
  71. 90ca14d Use MMCONF for all AMD family 10 CPUs. by Marc Jones · 13 years ago
  72. eafb18b Bootblock does not need a unique boot_cpu() by Kyösti Mälkki · 13 years ago
  73. 0dbfb54 Remove unused code files and cosmetic changes by Kyösti Mälkki · 13 years ago
  74. 04a8d62 k8 raminit: add workaround for erratum #181 on non-fam-f by Florian Zumbiehl · 13 years ago
  75. 2a40ebc Fix post_code in 16bit entry by Kyösti Mälkki · 13 years ago
  76. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  77. 784544b Remove XIP_ROM_BASE by Patrick Georgi · 13 years ago
  78. 9438da3 Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9 by Rudolf Marek · 13 years ago
  79. 914377e Get rid of the old romstage-as-bootblock ROM layout by Patrick Georgi · 13 years ago
  80. 1da1046 Get rid of AUTO_XIP_ROM_BASE by Patrick Georgi · 13 years ago
  81. 5460097 SPEEDSTEP: write _CST tables by Sven Schnelle · 13 years ago
  82. 521d8c2 Activate older Xeon P4 microcodes by Kyösti Mälkki · 13 years ago
  83. e2c05da Fixes several issues with amd k8 SSDT P-state generation by Oskar Enoksson · 13 years ago
  84. 3128685 SMM: Move wbinvd after pmode jump by Stefan Reinauer · 13 years ago
  85. 71496be Load an IDT with NULL limit by Stefan Reinauer · 13 years ago
  86. 07bf911 Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E by Oskar Enoksson · 13 years ago
  87. 8eb4273 Add AMD Family 10h PH-E0 support by QingPei Wang · 13 years ago
  88. 78834b7 Miscellaneous AMD F14 warning fixes by efdesign98 · 13 years ago
  89. ac624a6 Crank up CPU speed on Intel Core and Core2 CPUs by Patrick Georgi · 13 years ago
  90. f73535c AMD F14 Rev C0 update by Kerry She · 13 years ago
  91. 84cbce2 Update AMD F14 Agesa to support Rev C0 cpus by efdesign98 · 13 years ago
  92. 1ac19e2 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. by Keith Hui · 13 years ago
  93. 3cab93c Add SSE3 dependent code by efdesign98 · 13 years ago
  94. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  95. 4b50834 Add AMD Family 10 support to cpu folder by efdesign98 · 13 years ago
  96. b5b3b3b Make AMD SMM SMP aware by Rudolf Marek · 13 years ago
  97. 7f76290 Small SMM fixups by Rudolf Marek · 13 years ago
  98. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  99. 621ca38 Move existing AMD Ffamily14 code to f14 folder by efdesign98 · 13 years ago
  100. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago