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review.coreboot.org / coreboot / 296a015b8a99e611f68ee9836c8fb9dd054e325d / src / cpu
  1. e5fe3ac Fix typo in mPGA603 socket by Kyösti Mälkki · 12 years ago
  2. 0279036 Remove chip.h files without config structure by Kyösti Mälkki · 12 years ago
  3. 1fb49df C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA by Siyuan Wang · 12 years ago
  4. e644bad VIA Nano: Add support for VIA Nano CPUs by Alexandru Gagniuc · 12 years ago
  5. 00b579a buildsystem: Make CPU microcode updating more configurable by Alexandru Gagniuc · 12 years ago
  6. 0a78f91 Intel model_106cx: change CAR to HT-capable by Kyösti Mälkki · 12 years ago
  7. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  8. 9de0fee Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU by Kyösti Mälkki · 12 years ago
  9. dbc4739 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution by Kyösti Mälkki · 12 years ago
  10. 0db6820 Synchronize rdtsc instructions by Stefan Reinauer · 12 years ago
  11. 7bdf85b Move cpus_ready_for_init() to AMD K8 by Kyösti Mälkki · 12 years ago
  12. f85398c AMD S3: Remove the hardcoded volatile position by zbao · 12 years ago
  13. 57879c9 Make the device tree available in the rom stage by Stefan Reinauer · 12 years ago
  14. df0fbc7 Intel CPUs: Fix counting of CPU cores by Kyösti Mälkki · 12 years ago
  15. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  16. 51676b1 Revert "Use broadcast SIPI to startup siblings" by Sven Schnelle · 12 years ago
  17. a2701c6 Revert "remove CONFIG_SERIAL_CPU_INIT" by Sven Schnelle · 12 years ago
  18. 5563211 CPU: Add option to set TCC activation offset by Duncan Laurie · 12 years ago
  19. d6aca0b ACPI: Add a method to notify OS to re-read _PPC by Duncan Laurie · 12 years ago
  20. 0eefa00 ACPI: Add function to write _PPC using NVS by Duncan Laurie · 12 years ago
  21. 82704c6 USBDEBUG: buffer up to 8 bytes by Sven Schnelle · 12 years ago
  22. 0b7b7b6 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs by Stefan Reinauer · 12 years ago
  23. c65a36e Enable Microcode in CBFS for all SandyBridge/IvyBridge systems by Stefan Reinauer · 12 years ago
  24. 62f1ad9 SMM: Fix state table for Intel Core2 CPUs by Stefan Reinauer · 12 years ago
  25. c0f2cfb Fix comment to reference IvyBridge, too by Stefan Reinauer · 12 years ago
  26. 6d29c73 Include SandyBridge Microcode when IvyBridge is enabled by Stefan Reinauer · 12 years ago
  27. 0aa5b09 Fix date output in Microcode update by Stefan Reinauer · 12 years ago
  28. 8d32b89 Fix LAPIC timer on Ivy Bridge systems by Stefan Reinauer · 12 years ago
  29. 22935e1 CPU: Set flex ratio to nominal TDP ratio in bootblock by Duncan Laurie · 12 years ago
  30. 51cb26d SMM: Fix state save map for sandybridge and TSEG by Duncan Laurie · 12 years ago
  31. d2e00b9 SMM: Add heap region and move C handler higher in region by Duncan Laurie · 12 years ago
  32. 4e4320f CPU: Update ivybridge PP1 current limit value by Duncan Laurie · 12 years ago
  33. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  34. b91a0f2 Rename cache_lbmem() to cache_ramstage() by Stefan Reinauer · 12 years ago
  35. 999e94c Config changes to support microcode in CBFS by Vadim Bendebury · 12 years ago
  36. 39fea6e Add microcode blob processing by Vadim Bendebury · 12 years ago
  37. 537b4e0 Add code to read Intel microcode from CBFS by Vadim Bendebury · 12 years ago
  38. d81744e Make MAX_PHYSICAL_CPUS invisible on non-AMD boards by Stefan Reinauer · 12 years ago
  39. df0c822 Rename microcode include file to be model agnostic by Vadim Bendebury · 12 years ago
  40. b38e0c3 Properly identify ACPI C3 states in _CST table. by Duncan Laurie · 12 years ago
  41. 305b19d Remove code that enables/disables VMX in coreboot on chromebooks. by Ronald G. Minnich · 12 years ago
  42. 0067188 MTRR: drop repetetive debug message by Stefan Reinauer · 12 years ago
  43. ac2ec34 Re-initialize Local APIC timer on APs by Stefan Reinauer · 12 years ago
  44. a555e55 AMD CPUs: Updated CPU list in powernow_acpi.c by Jukka Rantala · 12 years ago
  45. 0728463 AMD northbridges: drop dead code by Kyösti Mälkki · 12 years ago
  46. de3dde4 AMD: Fix GFXUMA with 4GB or more RAM by Kyösti Mälkki · 12 years ago
  47. 2354515f AMD MTRR: fix rounding and renames by Kyösti Mälkki · 12 years ago
  48. 2d42b34 Check for IORESOURCE_UMA_FB in MTRR setup by Kyösti Mälkki · 12 years ago
  49. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  50. 22b7a55 Remove useless file from building. by zbao · 12 years ago
  51. ffc1fb3 Drop Kconfig VAR_MTRR_HOLE option by Kyösti Mälkki · 12 years ago
  52. 6f73a5b Fix stack assignment during CPU initialization by Sven Schnelle · 12 years ago
  53. 63539bb Only copy real-mode section of SIPI vector by Kyösti Mälkki · 12 years ago
  54. 9a663f3 Fix the CPU index parameter passed to secondary_cpu_init(). by Kyösti Mälkki · 12 years ago
  55. 5458b9d Intel cpus: Extend cache to cover complete Flash Device by Kyösti Mälkki · 12 years ago
  56. ae7d6ef Intel model_106cx: change CAR to model_6ex by Kyösti Mälkki · 12 years ago
  57. 4dcc573 Intel cpus: delete dead CAR code and whitespace fixes by Kyösti Mälkki · 12 years ago
  58. c7fb2ae Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR by Kyösti Mälkki · 12 years ago
  59. 2c08f6a AGESA F15 wrapper for Trinity by zbao · 12 years ago
  60. 78efc4c remove CONFIG_SERIAL_CPU_INIT by Sven Schnelle · 12 years ago
  61. 042c146 Use broadcast SIPI to startup siblings by Sven Schnelle · 12 years ago
  62. 9ed1456 Intel CPUs: execute microcode update only once per core by Kyösti Mälkki · 12 years ago
  63. edac28c Enable Intel PECI on Model 6fx CPUs by Sven Schnelle · 12 years ago
  64. 0860e72 udelay: add missing bus frequency by Sven Schnelle · 12 years ago
  65. 7c2d058 Fix the location of "Setting variable MTRR" printk. by Denis 'GNUtoo' Carikli · 12 years ago
  66. bb31f3a Drop config variable CPU_MODEL_INDEX by Stefan Reinauer · 12 years ago
  67. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  68. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  69. 3b5a9ed Fix register corruption during Intel Microcode update by Stefan Reinauer · 12 years ago
  70. 252111d Don't include console.h in microcode.c when compiling with ROMCC by Stefan Reinauer · 12 years ago
  71. 2c41c40 Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards by Stefan Reinauer · 12 years ago
  72. a1155b4 Move VSA support from x86 to Geode by Patrick Georgi · 12 years ago
  73. 943ddce Make geode_lx use the vsa from blobs repository by Patrick Georgi · 12 years ago
  74. c31384e Fix up Sandybridge C state generation code by Stefan Reinauer · 12 years ago
  75. 4cc8c70 Rework ACPI CST table generation by Stefan Reinauer · 12 years ago
  76. ae5e11d Move top level pc80 directory to drivers/ by Stefan Reinauer · 12 years ago
  77. 3110945 microcode: print date of microcode and unify output by Stefan Reinauer · 12 years ago
  78. 3f8989e Revamp Intel microcode update code by Stefan Reinauer · 12 years ago
  79. 05e740f Replace cache control magic numbers with symbols by Patrick Georgi · 12 years ago
  80. 1e6bf09 amd: Fix unused variable warning by Vikram Narayanan · 12 years ago
  81. d6e4d51 Revert wbind added to the reset_vector by Marc Jones · 12 years ago
  82. f722373 S3 code in coreboot public folder. by zbao · 12 years ago
  83. 3925622 S3 code in vendorcode folder. by zbao · 12 years ago
  84. 05758bd Remove obsolete empy macro definition by Ron Minnich · 12 years ago
  85. 2bdfb48 Fixes and Sandybridge support for lapic cpu init by Stefan Reinauer · 12 years ago
  86. f8c7c23 Fix support for RAM-less multi-processor init by Kyösti Mälkki · 12 years ago
  87. 334532e Add Sandybridge/Cougar Point support to SMM relocation handler by Stefan Reinauer · 12 years ago
  88. c00dfbc Cache 8MB flash instead of 4MB by Stefan Reinauer · 12 years ago
  89. 5b6404e Fix timer frequency detection on Sandybridge by Stefan Reinauer · 12 years ago
  90. deda997 Invalidate cache before first jump by Stefan Reinauer · 12 years ago
  91. 8c5b58e Update documentation in smmrelocate.S to mention TSEG by Stefan Reinauer · 12 years ago
  92. 5c55463 Add support for Intel Sandybridge CPU by Stefan Reinauer · 12 years ago
  93. 3aa067f Add support to run SMM handler in TSEG instead of ASEG by Stefan Reinauer · 12 years ago
  94. ea37a21 Add support for Intel Turbo Boost feature by Stefan Reinauer · 12 years ago
  95. abdf15f Apply cache-as-ram conditionally on socket mPGA604 by Kyösti Mälkki · 12 years ago
  96. afd141d S3 code whitespaces changes. by zbao · 12 years ago
  97. 819c7d4 Whitespace fixes by Patrick Georgi · 12 years ago
  98. a860c68 Intel cpus: get MAXPHYADDR at runtime for new CAR by Kyösti Mälkki · 12 years ago
  99. 0078ceb Intel cpus: add hyper-threading CPU support to new CAR by Kyösti Mälkki · 12 years ago
  100. 05d6ffb Intel cpus: improve CPU compatibility of new CAR by Kyösti Mälkki · 13 years ago