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review.coreboot.org / coreboot / 27d6299d51744bda549b7764b8fde909ad812e33 / src / northbridge / amd
  1. f722373 S3 code in coreboot public folder. by zbao · 12 years ago
  2. cab72d9 amdfam10: add phenom II as known cpu by Bernhard Urban · 12 years ago
  3. dd3b227 Fix AMD Fam15 CBMEM allocation by Stefan Reinauer · 12 years ago
  4. 30b46ce Fix AMD Fam12 CBMEM allocation by Stefan Reinauer · 12 years ago
  5. cc6c615 Fix AMD Fam10 CBMEM allocation by Stefan Reinauer · 12 years ago
  6. 3ae1c65 AMD Agesa: delete no-op bootblock files by Kyösti Mälkki · 12 years ago
  7. d11ca1d Rename AMD_AGESA to CPU_AMD_AGESA by Kyösti Mälkki · 12 years ago
  8. f5bb477 Fix AMD Agesa leaking Kconfig by Kyösti Mälkki · 12 years ago
  9. 35e1c86 VIA southbridge K8T890: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
  10. 5750ed2 Fix AMD Fam14 cbmen allocation by Marc Jones · 12 years ago
  11. 8d59569 Clean up whitespace in fam14 northbridge.c by Marc Jones · 12 years ago
  12. c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
  13. 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
  14. 472efa6 Remove whitespace. by Patrick Georgi · 13 years ago
  15. 6811f75 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper by Kerry Sheh · 13 years ago
  16. 6b909f2 RD890: AMD RD890/SR56X0 CIMX wrapper by Kerry Sheh · 13 years ago
  17. 976f8cc Make Geode GX2 VGA setup work. by Nils Jacobs · 13 years ago
  18. d0ac789 Update geode GX2 tree to match LX. by Nils Jacobs · 13 years ago
  19. 84e0dfc Clean up AMD Fam14 SSDT by Marc Jones · 13 years ago
  20. a4f06f1 White space and coding style fixes. by Nils Jacobs · 13 years ago
  21. 36b53bf k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x by Florian Zumbiehl · 13 years ago
  22. 2a830d0 Change AMD vendorcode build by Kyösti Mälkki · 13 years ago
  23. fa48b96 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 by Florian Zumbiehl · 13 years ago
  24. 6f7b158 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit by Florian Zumbiehl · 13 years ago
  25. 7e9de01 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 by Florian Zumbiehl · 13 years ago
  26. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  27. 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 13 years ago
  28. 86fc984 Fix compilation of AMD GX2 northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
  29. 80311ea amdk8: ASL include for K8 temperature sensor support in ACPI by Christoph Grenz · 13 years ago
  30. af90275 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms by enok71 · 13 years ago
  31. 8eb4273 Add AMD Family 10h PH-E0 support by QingPei Wang · 13 years ago
  32. 3f5ebd6 AMD F14 Northbridge updates by efdesign98 · 13 years ago
  33. feed329 AMD F14 southbridge update by Kerry She · 13 years ago
  34. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  35. b58640c Add AMD Family 10 cpu support to northbridge folder by efdesign98 · 13 years ago
  36. 7d6f0bf ASRock E350M1: ACPI-related BSOD fix by Scott Duplichan · 13 years ago
  37. 1fe6c64 Fix memory size reporting on AMD family 14h systems for >= 4GB by Cristian Măgherușan-Stanciu · 13 years ago
  38. 23b2152 Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and by Rudolf Marek · 13 years ago
  39. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  40. 621ca38 Move existing AMD Ffamily14 code to f14 folder by efdesign98 · 13 years ago
  41. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago
  42. 471f103 This patch sets max freq defaults for ddr2 and ddr3for fam10. by Marc Jones · 13 years ago
  43. 16c8e37 agesa_wrapper: Avoid repetitive Kconfig depends, trivial by Peter Stuge · 13 years ago
  44. 8c46263 Cosmetic cleanup. by Scott Duplichan · 13 years ago
  45. 5d878ad 1) Remove unused kconfig options. 2) Correct UMA graphics PCI device ID. by Scott Duplichan · 13 years ago
  46. 9ab3c6c Build device paths for AP cores so that coreboot will report them to the OS. by Scott Duplichan · 13 years ago
  47. dc312cc Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. by Scott Duplichan · 13 years ago
  48. 8d6cf3a Work around unclean CMOS handling for now by Patrick Georgi · 13 years ago
  49. b251753 Change read_option() to a macro that wraps some API uglyness by Patrick Georgi · 13 years ago
  50. d4814bd more ifdef -> if fixes by Stefan Reinauer · 13 years ago
  51. b18f9b0 The "temp" will be used later. So it has to be calculated correctly. by Zheng Bao · 13 years ago
  52. 432461e cleanup wrong use of defined() after exporting all variables in Kconfig by Stefan Reinauer · 13 years ago
  53. 5005bb06 Unify use of post_code by Alexandru Gagniuc · 13 years ago
  54. 2ca2f17 Add AMD C32 support. It is based on other existing Fam10 code. by Zheng Bao · 13 years ago
  55. 314dd0b Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. by Scott Duplichan · 13 years ago
  56. 11ac1cf Mark non-returning function as noreturn to help some compiler versions by Patrick Georgi · 13 years ago
  57. 6bdc83b Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  58. c313210 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  59. 6276b6f Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  60. 82b241a Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  61. 5bcedee Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  62. ce62350 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  63. e80ce0a Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  64. 26f97d2 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  65. 19245c9 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  66. e485aa4 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  67. 1f93fea Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  68. 0e5d3e1 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  69. adb23a5 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  70. 70a3733 Add 300 MHz and 500 MHz HT frequency limits by Xavi Drudis Ferran · 13 years ago
  71. ed1d116 Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS by Josef Kellermann · 13 years ago
  72. f0ccf6e Errata #169 works on HT, not MC by Josef Kellermann · 14 years ago
  73. 39fca80 This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code. by Frank Vibrans · 14 years ago
  74. 1df8542 Implemented workaround for erratum 169, obsoleting erratum 131. by Alexandru Gagniuc · 14 years ago
  75. dd676dd For Cx, each ChipSel need to be sent MR command. by Zheng Bao · 14 years ago
  76. c29675f Add a GX2 Kconfig option to choose the framebuffer size. by Nils Jacobs · 14 years ago
  77. a7296e7 The code is tested on my board with register DIMMs. More tests need to be by Zheng Bao · 14 years ago
  78. 69436e1 Fix some settings fo AMD MCT. It is based on BIOS test suite. by Zheng Bao · 14 years ago
  79. 8cf54c9 Use die() to assure the processor can't wake up from an interrupt. by Nils Jacobs · 14 years ago
  80. 84be0f5 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) by Nils Jacobs · 14 years ago
  81. 19d69e3 Move Geode GX2 UMA video memory size to Kconfig by Nils Jacobs · 14 years ago
  82. 642509c Remove dead and unused Geode GX2 code by Nils Jacobs · 14 years ago
  83. 3344743 Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names by Nils Jacobs · 14 years ago
  84. 1c6d4e6 Clean up Geode GX2 comments, whitespace and coding style. Trivial. by Nils Jacobs · 14 years ago
  85. cc1e645 Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. by Rudolf Marek · 14 years ago
  86. 59f410f Following patch adds support to bring out the memory out of self refresh when doing resume. by Rudolf Marek · 14 years ago
  87. 97be27e We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. by Rudolf Marek · 14 years ago
  88. 8677a23 After this has been brought up many times before, rename src/arch/i386 to by Stefan Reinauer · 14 years ago
  89. 8301d83 second round name simplification. drop the <component>_ prefix. by stepan · 14 years ago
  90. 1bc5cca Move MMCONF resource into the domain for fam10 for the resource allocator. by Myles Watson · 14 years ago
  91. ea62e9b More explicite and straight way to set seed. by Zheng Bao · 14 years ago
  92. bcaea14 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c by Rudolf Marek · 14 years ago
  93. abc0c85 Printing coreboot debug messages on VGA console is pretty much useless, since by Stefan Reinauer · 14 years ago
  94. d773fd3 Some more DIMM0 related cleanups and deduplication. by Uwe Hermann · 14 years ago
  95. 607614d Fix/drop some obsolete comments, by Uwe Hermann · 14 years ago
  96. e0c0a82 This problem was introduced with by Tobias Diedrich · 14 years ago
  97. f3cce2f MTRR related improvements for AMD family 10h and family 0Fh systems by Scott Duplichan · 14 years ago
  98. 02d66fd1b Make amdk8 printk_raminit() accept just a single string parameter by Peter Stuge · 14 years ago
  99. 7bbd7f2 Move K8_ALLOCATE_IO_RANGE to Kconfig. by Patrick Georgi · 14 years ago
  100. 00e1460 Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.c by Patrick Georgi · 14 years ago