- 2980e31 soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT by Sean Rhodes · 1 year, 4 months ago
- 076f861 Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT" by Michael Niewöhner · 1 year, 4 months ago
- 6bfca1b soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT by Sean Rhodes · 1 year, 6 months ago
- 3e86681 soc/intel/tigerlake: Use common gpio.h include by Dinesh Gehlot · 1 year, 7 months ago
- 9395cf9 soc/intel: Create common function to check PCH slot by Kapil Porwal · 1 year, 8 months ago
- 9018dee src/soc/intel: Remove unnecessary space after casts by Elyes Haouas · 1 year, 9 months ago
- cbbbb6c soc/intel/tigerlake: Clean up includes by Elyes Haouas · 1 year, 10 months ago
- 82f0a68 soc/intel/tigerlake/fsp_params.c: Add INT D routing for PEG60 by Frans Hendriks · 2 years ago
- f4040e6 soc/intel/tigerlake: Add USBOTG and CrashLog to irq table by Frans Hendriks · 2 years ago
- 5960978 soc/intel/tgl: Add PEG devices to PCI constraints by Tim Crawford · 2 years, 3 months ago
- 45b6080 soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented by Michael Niewöhner · 2 years, 7 months ago
- f424c8b soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()` by Felix Singer · 2 years, 8 months ago
- 2aa1ff4 soc/intel/tigerlake: Hook up DPTF device to devicetree by Felix Singer · 2 years, 9 months ago
- e8b6b07 intel/tigerlake: Add missing IRQ for CNVi by Sean Rhodes · 2 years, 10 months ago
- 0e90580 soc/intel: transition full control over PM Timer from FSP to coreboot by Michael Niewöhner · 2 years, 11 months ago
- 298b359 drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method by Subrata Banik · 3 years ago
- 90f9cbb soc/intel/tigerlake: Move LPM functions to new file by Tim Wawrzynczak · 3 years, 1 month ago
- 5896608 soc/intel/tigerlake: Lock PAM registers in finalize by Tim Wawrzynczak · 3 years ago
- 21d7c47 soc/intel/tigerlake: Add PCH-H GPIO definitions by Jeremy Soller · 3 years ago
- 673e6d1 soc/intel/tigerlake: Clean up FSP chipset lockdown configuration by Felix Singer · 3 years, 4 months ago
- f3c4f29 soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S by Tim Crawford · 3 years ago
- bc35bed soc/intel/*: Allow configuring 8254 timer via CMOS by Sean Rhodes · 3 years, 1 month ago
- aec0716 soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' by Subrata Banik · 3 years, 1 month ago
- c7cfe0b soc/intel: Refactor `xdci_can_enable()` function by Angel Pons · 3 years, 2 months ago
- 25d2452 soc/intel/tigerlake: Send End-of-Post message to CSE by Tim Wawrzynczak · 3 years, 2 months ago
- ed042a9 soc/intel/tigerlake: Enable support for common IRQ block by Tim Wawrzynczak · 3 years, 6 months ago
- c3a5c05 soc/intel/tigerlake: Use devfn_disable() function for XDCI by Subrata Banik · 3 years, 2 months ago
- 49a2109 soc/intel/tigerlake: Make use of is_devfn_enabled() function by Subrata Banik · 3 years, 2 months ago
- 3e3c456 soc/intel/tigerlake: Hook up FSP repository by Felix Singer · 3 years, 8 months ago
- b9b6f4d soc/intel: Drop unused lpss functions by Furquan Shaikh · 3 years, 2 months ago
- 4b3e06e soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC by Nick Vaccaro · 3 years, 3 months ago
- 59a621a soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads by Tim Wawrzynczak · 3 years, 5 months ago
- 82d5123 intel/tigerlake: Add Acoustic features by Shaunak Saha · 3 years, 6 months ago
- eb6ebc0 soc/intel/tigerlake: Move TCSS code to intel/common/block by Tim Wawrzynczak · 3 years, 5 months ago
- 8056187 soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable by Derek Huang · 3 years, 5 months ago
- b34be4d soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry by Cliff Huang · 3 years, 6 months ago
- d8774f6 soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot by Brandon Breitenstein · 3 years, 6 months ago
- 2914455 soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and soc by Brandon Breitenstein · 3 years, 9 months ago
- 202b189 soc/intel/tigerlake: Enable end of post support in FSP by Nick Vaccaro · 3 years, 6 months ago
- fbad99f soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design by Shreesh Chhabbi · 3 years, 7 months ago
- bf50c31 soc/intel/tgl: Add configurable value for UsbTcPortEn by Brandon Breitenstein · 3 years, 8 months ago
- 44509d8 soc/intel/tigerlake: Disable TC cold support by Srinidhi N Kaushik · 3 years, 7 months ago
- 4ead6b33 soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports by John Zhao · 3 years, 8 months ago
- 17e905ac soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement by Duncan Laurie · 3 years, 10 months ago
- 99b38a9 soc/intel/tigerlake: Add code for early tcss by Brandon Breitenstein · 4 years, 8 months ago
- d83e24d soc/intel/tigerlake: Disable C1 C-state Demotion by Ravi Sarawadi · 3 years, 10 months ago
- 0d0f43f soc/intel/tigerlake: Add Acoustic features by Shaunak Saha · 4 years ago
- c16fc8a soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffload by John Zhao · 4 years ago
- 5b7daa2 soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths by Jamie Ryu · 4 years ago
- 056d552 soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default by Michael Niewöhner · 4 years ago
- 476ca3a soc/intel/tigerlake: Add mainboard hook for overriding SoC config by Jes Klinke · 4 years ago
- 6fd87ff soc/intel/tigerlake: Allow fine grained control of S0iX states by Jes Klinke · 4 years ago
- 6362de3 soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated by Subrata Banik · 4 years, 1 month ago
- bd615d6 soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold by John Zhao · 4 years, 1 month ago
- 5c10704 soc/intel/tigerlake: Simplify is-device-enabled checks by Felix Singer · 4 years, 1 month ago
- c25c1eb src: Update bare access to BOOL CONFIG_ vals to CONFIG() by Martin Roth · 4 years, 1 month ago
- b622d4b soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2 by Subrata Banik · 4 years, 3 months ago
- 1a8949c soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs by Shaunak Saha · 4 years, 2 months ago
- 02a1b33 soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot by Jamie Ryu · 4 years, 2 months ago
- 6caa476 tigerlake: enable tcc_offset functionality by Sumeet R Pawnikar · 4 years, 2 months ago
- c66c153 soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD by Wonkyu Kim · 4 years, 3 months ago
- e18f719 soc/intel/tigerlake: Add devicetree support to change PCH VR settings by Venkata Krishna Nimmagadda · 4 years, 3 months ago
- 92a3a30 soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs by John Zhao · 4 years, 3 months ago
- 4cabf78 soc/intel/tigerlake: Configure THC by Wonkyu Kim · 4 years, 3 months ago
- 165efa1 soc/intel/tigerlake: Disable VMD by Wonkyu Kim · 4 years, 3 months ago
- 8aac881 soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable by John Zhao · 4 years, 3 months ago
- 7d6bc60 tigerlake: enable DPTF functionality for volteer by Sumeet R Pawnikar · 4 years, 3 months ago
- 71d365d soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg by Brandon Breitenstein · 4 years, 4 months ago
- 32b8a51 soc/intel/tigerlake: Control SATA and DMI power optimization by Shaunak Saha · 4 years, 5 months ago
- 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
- 0d6cc22 soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree by Meera Ravindranath · 4 years, 4 months ago
- 82e0a81 soc/intel/tigerlake: Merge the recent change from other platforms by Wonkyu Kim · 4 years, 4 months ago
- 3ba64ca soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN by Wonkyu Kim · 4 years, 5 months ago
- 5943117 soc/intel/tigerlake: Configure RP setting by Wonkyu Kim · 4 years, 4 months ago
- 16f6aa8 soc/intel/tigerlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 4 months ago
- 555c9b6 soc/intel/tigerlake: Remove Jasper Lake SoC references by Aamir Bohra · 4 years, 5 months ago[Renamed from src/soc/intel/tigerlake/fsp_params_tgl.c]
- fc93237 soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3 by Brandon Breitenstein · 4 years, 5 months ago
- 1163745 soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT by Brandon Breitenstein · 4 years, 6 months ago
- 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
- a6bff2d soc/intel/tigerlake: Enable CNVi through dev_enabled by Srinidhi N Kaushik · 4 years, 5 months ago
- 84b4882 soc/intel/tigerlake: Configure L1Substates for PCH Root ports by Wonkyu Kim · 4 years, 5 months ago
- 2b4ded0 soc/intel/tigerlake: Enable Hybrid storage mode by Wonkyu Kim · 4 years, 6 months ago
- 8488853 soc/intel/tigerlake: Enable CNVi Mode by Srinidhi N Kaushik · 4 years, 6 months ago
- ad64781 soc/intel/tigerlake: Avoid NULL pointer dereference by John Zhao · 4 years, 6 months ago
- 4af0adb soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake by Srinidhi N Kaushik · 4 years, 6 months ago
- b3fa6a0 soc/intel/tigerlake: configure ethernet by Wonkyu Kim · 4 years, 6 months ago
- 1bfd56cb soc/intel/tigerlake: Integrate Legacy 8254 timer support by Subrata Banik · 4 years, 6 months ago
- 815d96a soc/intel/tigerlake: Enable SATA by Wonkyu Kim · 4 years, 7 months ago
- d801b1f soc/intel/tigerlake: Update fsp_params for TGL by Srinidhi N Kaushik · 4 years, 8 months ago
- 50ee91c soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig by Maulik V Vaghela · 4 years, 9 months ago[Copied from src/soc/intel/tigerlake/fsp_params.c]
- 86da00d soc/intel/tigerlake: Include soc common lpss header file by Aamir Bohra · 4 years, 9 months ago
- 91e89c5 soc/intel/tigerlake: Do initial SoC commit till ramstage by Subrata Banik · 4 years, 10 months ago