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review.coreboot.org / coreboot / 016cc4296e7040c60c741b186d6b3e87a688421c / src / mainboard / siemens / mc_apl1 / variants
  1. 016cc42 siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read by Mario Scheithauer · 6 years ago
  2. 697faf0 siemens/mc_apl4: Set CPU clock to minimum ratio by Werner Zeh · 6 years ago
  3. 5716b4c siemens/mc_apl5: Add new mainboard variant mc_apl5 by Mario Scheithauer · 6 years ago
  4. a5f5790 mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR by Elyes HAOUAS · 6 years ago
  5. f765d4f src: Remove unneeded include <lib.h> by Elyes HAOUAS · 6 years ago
  6. 395cbb4 mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree by Peter Lemenkov · 6 years ago
  7. 5f82433 siemens/mc_apl4: Clean up ramstage by Mario Scheithauer · 6 years ago
  8. 6c52c0b siemens/mc_apl4: Overwrite swizzle data for LPDDR4 by Mario Scheithauer · 6 years ago
  9. 5d69297 siemens/mc_apl4: Enable SDCARD by Mario Scheithauer · 6 years ago
  10. adc7d8e siemens/mc_apl4: Remove external RTC from I2C0 by Mario Scheithauer · 6 years ago
  11. 3a49972 siemens/mc_apl4: Enable all PCIe root ports by Mario Scheithauer · 6 years ago
  12. fe73678 siemens/mc_apl4: Remove reduced clock rate for I2C0 by Mario Scheithauer · 6 years ago
  13. c27ce82 siemens/mc_apl4: Disable CLKREQ of PCIe root ports by Mario Scheithauer · 6 years ago
  14. 4946804 siemens/mc_apl3: Disable PCI clock outputs on XIO bridges by Mario Scheithauer · 6 years ago
  15. 04ea73e siemens/mc_apl3: Set Full Reset Bit into Reset Control Register by Mario Scheithauer · 6 years ago
  16. d985cdc siemens/mc_apl3: Set bus master bit for on-board PCI device by Mario Scheithauer · 6 years ago
  17. bcbcecd siemens/mc_apl3: Remove the correction of the Tx signal for SATA by Mario Scheithauer · 6 years ago
  18. 98689df siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices by Mario Scheithauer · 6 years ago
  19. e510f21 siemens/mc_apl4: Add new mainboard variant mc_apl4 by Mario Scheithauer · 6 years ago
  20. 84672a9 siemens/mc_apl2: Adjust GPIO settings for mc_apl2 by Mario Scheithauer · 6 years ago
  21. c776609 siemens/mc_apl3: Disable I2C7 over devicetree by Mario Scheithauer · 6 years ago
  22. f76acba siemens/mc_apl3: Enable all PCIe root ports by Mario Scheithauer · 6 years ago
  23. 87f8839 siemens/mc_apl3: Remove reduced clock rate for I2C0 by Mario Scheithauer · 6 years ago
  24. 0d0ebb6 siemens/mc_apl3: Disable CLKREQ of PCIe root ports by Mario Scheithauer · 6 years ago
  25. a29d4d2 siemens/mc_apl3: Adjust GPIO settings for mc_apl3 by Mario Scheithauer · 6 years ago
  26. 58bf3e7 siemens/mc_apl3: Add new mainboard variant mc_apl3 by Mario Scheithauer · 6 years ago
  27. d44221f Move compiler.h to commonlib by Nico Huber · 6 years ago
  28. 6bedbd6 soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD by Furquan Shaikh · 6 years ago
  29. 1e67f07 siemens/mc_apl1: Activate clock spreading for PTN3460 by Mario Scheithauer · 6 years ago
  30. 66038c8 siemens/mc_apl1: Add new mainboard variant mc_apl2 by Mario Scheithauer · 6 years ago
  31. 7e15e87 siemens/mc_apl1: Make the DDR memory swizzle data configurable by Mario Scheithauer · 6 years ago
  32. e27c096 siemens/mc_apl1: Correct the Tx signal from SATA interface by Mario Scheithauer · 6 years ago
  33. 403458e siemens/mc_apl1: Extend circuit life by clock gating and power gating by Mario Scheithauer · 6 years ago
  34. 5650896 siemens/mc_apl1: Disable PCI clock outputs on XIO bridge by Mario Scheithauer · 6 years ago
  35. 16ebc98 siemens/mc_apl1: Select DDR50 mode for eMMC by Mario Scheithauer · 6 years ago
  36. 0e1a526 siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard by Mario Scheithauer · 6 years ago
  37. 053851f siemens/mc_apl1: Move board specific things to mc_apl1 variant by Mario Scheithauer · 6 years ago
  38. c4986eb soc/intel/common/block: Add common chip config block by Subrata Banik · 6 years ago
  39. 6141353 siemens/mc_apl1: Move board specific things to mc_apl1 variant by Mario Scheithauer · 6 years ago
  40. d127be1 siemens/mc_apl1: Provide baseboard and variant concepts by Mario Scheithauer · 6 years ago