| commit | 56508967d8b433b2821d54207370332e1f319354 | [log] [tgz] |
|---|---|---|
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | Thu Aug 23 14:48:06 2018 +0200 |
| committer | Werner Zeh <werner.zeh@siemens.com> | Mon Aug 27 06:31:27 2018 +0000 |
| tree | 136e5408a17b0d396a659a421f070fa24e5a54b5 | |
| parent | c5cca15cce060699256cb7f81aeefb39065ac3bd [diff] |
siemens/mc_apl1: Disable PCI clock outputs on XIO bridge This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge. Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>