siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard

For the 1st redesign of mc_apl1 mainboard some adjustments are

- The FPGA is now connected directly via a PCIe Root Port
- Internal Apollo Lake UARTs are now used
- Adjusting GPIO settings

Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57
Signed-off-by: Mario Scheithauer <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Werner Zeh <>
2 files changed