Blame - src/northbridge/intel/i945/chip.h - coreboot

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Angel Pons	4b42983	2020-04-02 23:48:50 +0200	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0-only */
Martin Roth	5474eb1	2018-05-26 19:22:33 -0600	[diff] [blame]	2
Iru Cai	d7ee9dd	2016-02-24 15:03:58 +0800	[diff] [blame]	3	#ifndef NORTHBRIDGE_INTEL_I945_CHIP_H
				4	#define NORTHBRIDGE_INTEL_I945_CHIP_H
				5
Vladimir Serbinenko	dd2bc3f	2014-10-31 09:16:31 +0100	[diff] [blame]	6	#include <drivers/intel/gma/i915.h>
Elyes Haouas	a521d66	2022-11-30 07:51:11 +0100	[diff] [blame]	7	#include <types.h>
Vladimir Serbinenko	dd2bc3f	2014-10-31 09:16:31 +0100	[diff] [blame]	8
Vladimir Serbinenko	26ca08c	2014-06-01 00:24:05 +0200	[diff] [blame]	9	struct northbridge_intel_i945_config {
Arthur Heymans	8e07900	2017-01-14 22:31:54 +0100	[diff] [blame]	10	/* In units of 100us timer */
				11	/* Timings as defined in VESA Notebook Panel Standard */
				12	u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
				13	u16 gpu_panel_power_down_delay; /* T3 time sequence */
				14	u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
				15	u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
				16	/* In units of 0.1s */
				17	u8 gpu_panel_power_cycle_delay;
				18
Vladimir Serbinenko	26ca08c	2014-06-01 00:24:05 +0200	[diff] [blame]	19	u32 gpu_hotplug;
Arthur Heymans	8e07900	2017-01-14 22:31:54 +0100	[diff] [blame]	20	u32 pwm_freq;
Elyes Haouas	a521d66	2022-11-30 07:51:11 +0100	[diff] [blame]	21	bool gpu_lvds_use_spread_spectrum_clock;
Vladimir Serbinenko	dd2bc3f	2014-10-31 09:16:31 +0100	[diff] [blame]	22	struct i915_gpu_controller_info gfx;
Arthur Heymans	885c289	2016-10-03 17:16:48 +0200	[diff] [blame]	23	int pci_mmio_size;
Vladimir Serbinenko	26ca08c	2014-06-01 00:24:05 +0200	[diff] [blame]	24	};
Iru Cai	d7ee9dd	2016-02-24 15:03:58 +0800	[diff] [blame]	25
				26	#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */