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Iru Caid7ee9dd2016-02-24 15:03:58 +08001#ifndef NORTHBRIDGE_INTEL_I945_CHIP_H
2#define NORTHBRIDGE_INTEL_I945_CHIP_H
3
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01004#include <drivers/intel/gma/i915.h>
5
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +02006struct northbridge_intel_i945_config {
Arthur Heymans8e079002017-01-14 22:31:54 +01007 /* In units of 100us timer */
8 /* Timings as defined in VESA Notebook Panel Standard */
9 u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
10 u16 gpu_panel_power_down_delay; /* T3 time sequence */
11 u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
12 u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
13 /* In units of 0.1s */
14 u8 gpu_panel_power_cycle_delay;
15
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020016 u32 gpu_hotplug;
Arthur Heymans8e079002017-01-14 22:31:54 +010017 u32 pwm_freq;
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020018 int gpu_lvds_use_spread_spectrum_clock;
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010019 struct i915_gpu_controller_info gfx;
Arthur Heymans885c2892016-10-03 17:16:48 +020020 int pci_mmio_size;
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020021};
Iru Caid7ee9dd2016-02-24 15:03:58 +080022
23#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */