blob: 8078c9c386948f75ef73c31463d6c65ffbe0e140 [file] [log] [blame]
Angel Pons1c9a8d82022-05-07 00:26:10 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#ifndef HASWELL_RAMINIT_NATIVE_H
4#define HASWELL_RAMINIT_NATIVE_H
5
Angel Pons1b254222022-05-07 13:48:53 +02006#include <device/dram/ddr3.h>
7#include <northbridge/intel/haswell/haswell.h>
8
Elyes Haouasca3764a2024-05-12 11:50:08 +02009/** TODO (Angel): Remove this after in-review patches are submitted **/
10#define SPD_LEN SPD_SIZE_MAX_DDR3
Angel Pons1b254222022-05-07 13:48:53 +020011
12/* 8 data lanes + 1 ECC lane */
13#define NUM_LANES 9
14#define NUM_LANES_NO_ECC 8
15
Angel Pons1c9a8d82022-05-07 00:26:10 +020016enum raminit_boot_mode {
17 BOOTMODE_COLD,
18 BOOTMODE_WARM,
19 BOOTMODE_S3,
20 BOOTMODE_FAST,
21};
22
23enum raminit_status {
24 RAMINIT_STATUS_SUCCESS = 0,
Angel Pons1b254222022-05-07 13:48:53 +020025 RAMINIT_STATUS_NO_MEMORY_INSTALLED,
26 RAMINIT_STATUS_UNSUPPORTED_MEMORY,
Angel Pons1c9a8d82022-05-07 00:26:10 +020027 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
28};
29
30enum generic_stepping {
31 STEPPING_A0 = 1,
32 STEPPING_B0 = 2,
33 STEPPING_C0 = 3,
34};
35
Angel Pons1b254222022-05-07 13:48:53 +020036struct raminit_dimm_info {
Elyes Haouas78ba7a72024-05-06 05:11:28 +020037 spd_ddr3_raw_data raw_spd;
Angel Pons1b254222022-05-07 13:48:53 +020038 struct dimm_attr_ddr3_st data;
39 uint8_t spd_addr;
40 bool valid;
41};
42
Angel Pons1c9a8d82022-05-07 00:26:10 +020043struct sysinfo {
44 enum raminit_boot_mode bootmode;
45 enum generic_stepping stepping;
46 uint32_t cpu; /* CPUID value */
47
48 bool dq_pins_interleaved;
Angel Pons1b254222022-05-07 13:48:53 +020049
50 /** TODO: ECC support untested **/
51 bool is_ecc;
52
53 /**
54 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
55 * but some LPDDR-specific variations in algorithms have been handled.
56 * LPDDR-specific functions have stubs which will halt upon execution.
57 */
58 bool lpddr;
59
60 struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
61 union dimm_flags_ddr3_st flags;
62 uint16_t cas_supported;
63
64 /* Except for tCK, everything is eventually stored in DCLKs */
65 uint32_t tCK;
66 uint32_t tAA; /* Also known as tCL */
67 uint32_t tWR;
68 uint32_t tRCD;
69 uint32_t tRRD;
70 uint32_t tRP;
71 uint32_t tRAS;
72 uint32_t tRC;
73 uint32_t tRFC;
74 uint32_t tWTR;
75 uint32_t tRTP;
76 uint32_t tFAW;
77 uint32_t tCWL;
78 uint32_t tCMD;
79
80 uint8_t lanes; /* 8 or 9 */
81 uint8_t chanmap;
82 uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */
83 uint8_t rankmap[NUM_CHANNELS];
84 uint8_t rank_mirrored[NUM_CHANNELS];
85 uint32_t channel_size_mb[NUM_CHANNELS];
Angel Pons1c9a8d82022-05-07 00:26:10 +020086};
87
88void raminit_main(enum raminit_boot_mode bootmode);
89
Angel Pons1b254222022-05-07 13:48:53 +020090enum raminit_status collect_spd_info(struct sysinfo *ctrl);
91
Angel Pons1c9a8d82022-05-07 00:26:10 +020092#endif