nb/intel/haswell: Add native raminit scaffolding
Implement some scaffolding for Haswell native raminit, like bootmode
selection, handling of MRC cache and CPU detection.
Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
new file mode 100644
index 0000000..885f018
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_RAMINIT_NATIVE_H
+#define HASWELL_RAMINIT_NATIVE_H
+
+enum raminit_boot_mode {
+ BOOTMODE_COLD,
+ BOOTMODE_WARM,
+ BOOTMODE_S3,
+ BOOTMODE_FAST,
+};
+
+enum raminit_status {
+ RAMINIT_STATUS_SUCCESS = 0,
+ RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+};
+
+enum generic_stepping {
+ STEPPING_A0 = 1,
+ STEPPING_B0 = 2,
+ STEPPING_C0 = 3,
+};
+
+struct sysinfo {
+ enum raminit_boot_mode bootmode;
+ enum generic_stepping stepping;
+ uint32_t cpu; /* CPUID value */
+
+ bool dq_pins_interleaved;
+};
+
+void raminit_main(enum raminit_boot_mode bootmode);
+
+#endif