Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | // Use simple device model for this file even in ramstage |
| 4 | #define __SIMPLE_DEVICE__ |
| 5 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 6 | #include <arch/romstage.h> |
| 7 | #include <cbmem.h> |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 8 | #include <cpu/intel/smm_reloc.h> |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 9 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 10 | #include <cpu/x86/smm.h> |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 12 | #include <program_loading.h> |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 13 | #include <stdint.h> |
| 14 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 15 | #include "e7505.h" |
| 16 | |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 17 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
| 18 | |
| 19 | static uintptr_t top_of_low_ram(void) |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 20 | { |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 21 | uintptr_t tolm; |
| 22 | |
| 23 | /* This is at 128 MiB boundary. */ |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 24 | tolm = pci_read_config16(HOST_BRIDGE, TOLM) >> 11; |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 25 | tolm <<= 27; |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 26 | return tolm; |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 27 | } |
| 28 | |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 29 | size_t northbridge_get_tseg_size(void) |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 30 | { |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 31 | const uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); |
| 32 | |
| 33 | if (!(esmramc & T_EN)) |
| 34 | return 0; |
| 35 | |
| 36 | switch ((esmramc & TSEG_SZ_MASK) >> 1) { |
| 37 | case 0: |
| 38 | return 128 * KiB; |
| 39 | case 1: |
| 40 | return 256 * KiB; |
| 41 | case 2: |
| 42 | return 512 * KiB; |
| 43 | case 3: |
| 44 | default: |
| 45 | return 1 * MiB; |
| 46 | } |
| 47 | } |
| 48 | |
| 49 | uintptr_t northbridge_get_tseg_base(void) |
| 50 | { |
| 51 | uintptr_t tolm = top_of_low_ram(); |
| 52 | |
| 53 | /* subtract TSEG size */ |
| 54 | tolm -= northbridge_get_tseg_size(); |
| 55 | return tolm; |
| 56 | } |
| 57 | |
| 58 | void smm_region(uintptr_t *start, size_t *size) |
| 59 | { |
| 60 | *start = northbridge_get_tseg_base(); |
| 61 | *size = northbridge_get_tseg_size(); |
| 62 | } |
| 63 | |
| 64 | uintptr_t cbmem_top_chipset(void) |
| 65 | { |
| 66 | return northbridge_get_tseg_base(); |
| 67 | } |
| 68 | |
| 69 | void smm_open(void) |
| 70 | { |
| 71 | /* Set D_OPEN */ |
| 72 | pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG); |
| 73 | } |
| 74 | |
| 75 | void smm_close(void) |
| 76 | { |
| 77 | /* Clear D_OPEN */ |
| 78 | pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG); |
| 79 | } |
| 80 | |
| 81 | void smm_lock(void) |
| 82 | { |
| 83 | /* |
| 84 | * LOCK the SMM memory window and enable normal SMM. |
| 85 | * After running this function, only a full reset can |
| 86 | * make the SMM registers writable again. |
| 87 | */ |
| 88 | printk(BIOS_DEBUG, "Locking SMM.\n"); |
| 89 | |
| 90 | pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 94 | { |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 95 | /* |
| 96 | * Choose to NOT set ROM as WP cacheable here. |
| 97 | * Timestamps indicate the CPU this northbridge code is |
| 98 | * connected to, performs better for memcpy() and un-lzma |
| 99 | * operations when source is left as UC. |
| 100 | */ |
| 101 | |
| 102 | pcf->skip_common_mtrr = 1; |
| 103 | |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 104 | /* Cache RAM as WB from 0 -> TOLM. */ |
| 105 | postcar_frame_add_mtrr(pcf, top_of_low_ram(), CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 106 | } |