Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | // Use simple device model for this file even in ramstage |
| 4 | #define __SIMPLE_DEVICE__ |
| 5 | |
| 6 | #include <device/pci_ops.h> |
| 7 | #include <arch/romstage.h> |
| 8 | #include <cbmem.h> |
| 9 | #include <cpu/x86/mtrr.h> |
| 10 | #include <program_loading.h> |
| 11 | #include "e7505.h" |
| 12 | |
| 13 | void *cbmem_top_chipset(void) |
| 14 | { |
| 15 | const pci_devfn_t mch = PCI_DEV(0, 0, 0); |
| 16 | uintptr_t tolm; |
| 17 | |
| 18 | /* This is at 128 MiB boundary. */ |
| 19 | tolm = pci_read_config16(mch, TOLM) >> 11; |
| 20 | tolm <<= 27; |
| 21 | |
| 22 | return (void *)tolm; |
| 23 | } |
| 24 | |
| 25 | void northbridge_write_smram(u8 smram); |
| 26 | |
| 27 | void northbridge_write_smram(u8 smram) |
| 28 | { |
| 29 | const pci_devfn_t mch = PCI_DEV(0, 0, 0); |
| 30 | pci_write_config8(mch, SMRAMC, smram); |
| 31 | } |
| 32 | |
| 33 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 34 | { |
| 35 | uintptr_t top_of_ram; |
| 36 | |
| 37 | /* |
| 38 | * Choose to NOT set ROM as WP cacheable here. |
| 39 | * Timestamps indicate the CPU this northbridge code is |
| 40 | * connected to, performs better for memcpy() and un-lzma |
| 41 | * operations when source is left as UC. |
| 42 | */ |
| 43 | |
| 44 | pcf->skip_common_mtrr = 1; |
| 45 | |
| 46 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 47 | postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 48 | |
| 49 | /* Cache CBMEM region as WB. */ |
| 50 | top_of_ram = (uintptr_t)cbmem_top(); |
| 51 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, |
| 52 | MTRR_TYPE_WRBACK); |
| 53 | } |