Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <console/console.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 24 | #include <cbmem.h> |
| 25 | #include <northbridge/intel/pineview/pineview.h> |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 26 | #include <cpu/x86/mtrr.h> |
| 27 | #include <cpu/intel/romstage.h> |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 28 | #include <cpu/intel/smm/gen1/smi.h> |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 29 | #include <stdint.h> |
| 30 | #include <stage_cache.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 31 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 32 | u8 decode_pciebar(u32 *const base, u32 *const len) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 33 | { |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 34 | *base = 0; |
| 35 | *len = 0; |
| 36 | const pci_devfn_t dev = PCI_DEV(0,0,0); |
| 37 | u32 pciexbar = 0; |
| 38 | u32 pciexbar_reg; |
| 39 | u32 reg32; |
| 40 | int max_buses; |
| 41 | const struct { |
| 42 | u16 num_buses; |
| 43 | u32 addr_mask; |
| 44 | } busmask[] = { |
| 45 | {256, 0xf0000000}, |
| 46 | {128, 0xf8000000}, |
| 47 | {64, 0xfc000000}, |
| 48 | {0, 0}, |
| 49 | }; |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 50 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 51 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
| 52 | |
| 53 | // MMCFG not supported or not enabled. |
| 54 | if (!(pciexbar_reg & (1 << 0))) { |
| 55 | printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); |
| 56 | return 0; |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 57 | } |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 58 | |
| 59 | reg32 = (pciexbar_reg >> 1) & 3; |
| 60 | pciexbar = pciexbar_reg & busmask[reg32].addr_mask; |
| 61 | max_buses = busmask[reg32].num_buses; |
| 62 | |
| 63 | if (!pciexbar) { |
| 64 | printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | *base = pciexbar; |
| 69 | *len = max_buses << 20; |
| 70 | return 1; |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 71 | } |
| 72 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 73 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 74 | u32 decode_igd_memory_size(const u32 gms) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 75 | { |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 76 | const u32 gmssize[] = { |
| 77 | 0, 1, 4, 8, 16, 32, 48, 64, 128, 256 |
| 78 | }; |
| 79 | |
| 80 | if (gms > 9) { |
| 81 | printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n"); |
| 82 | return 0; |
| 83 | } |
| 84 | return gmssize[gms] << 10; |
| 85 | } |
| 86 | |
| 87 | /** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ |
| 88 | u32 decode_igd_gtt_size(const u32 gsm) |
| 89 | { |
| 90 | const u8 gsmsize[] = { |
| 91 | 0, 1, 0, 0, |
| 92 | }; |
| 93 | |
| 94 | if (gsm > 3) { |
| 95 | printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n"); |
| 96 | return 0; |
| 97 | } |
| 98 | return (u32)(gsmsize[gsm] << 10); |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 99 | } |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 100 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 101 | /** Decodes used TSEG size to bytes. */ |
| 102 | static u32 decode_tseg_size(const u32 esmramc) |
| 103 | { |
| 104 | if (!(esmramc & 1)) |
| 105 | return 0; |
| 106 | |
| 107 | switch ((esmramc >> 1) & 3) { |
| 108 | case 0: |
| 109 | return 1 << 20; |
| 110 | case 1: |
| 111 | return 2 << 20; |
| 112 | case 2: |
| 113 | return 8 << 20; |
| 114 | case 3: |
| 115 | default: |
| 116 | die("Bad TSEG setting.\n"); |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | u32 northbridge_get_tseg_size(void) |
| 121 | { |
| 122 | const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); |
| 123 | return decode_tseg_size(esmramc); |
| 124 | } |
| 125 | |
| 126 | u32 northbridge_get_tseg_base(void) |
| 127 | { |
| 128 | return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); |
| 129 | } |
| 130 | |
| 131 | |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 132 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
Elyes HAOUAS | 64f6b71 | 2018-08-07 12:16:56 +0200 | [diff] [blame] | 133 | * 1 MiB alignment. As this may cause very greedy MTRR setup, push |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 134 | * CBMEM top downwards to 4 MiB boundary. |
| 135 | */ |
| 136 | void *cbmem_top(void) |
| 137 | { |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 138 | uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 139 | return (void *) top_of_ram; |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 140 | |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 141 | } |
| 142 | |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 143 | void stage_cache_external_region(void **base, size_t *size) |
| 144 | { |
Kyösti Mälkki | bccd2b6 | 2019-08-02 06:12:03 +0300 | [diff] [blame] | 145 | /* The stage cache lives at the end of the TSEG region. |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 146 | * The top of RAM is defined to be the TSEG base address. |
| 147 | */ |
| 148 | *size = CONFIG_SMM_RESERVED_SIZE; |
Kyösti Mälkki | bccd2b6 | 2019-08-02 06:12:03 +0300 | [diff] [blame] | 149 | *base = (void *)((uintptr_t)northbridge_get_tseg_base() |
| 150 | + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 151 | } |
| 152 | |
Arthur Heymans | aa7cf55 | 2018-06-03 10:44:55 +0200 | [diff] [blame] | 153 | /* platform_enter_postcar() determines the stack to use after |
| 154 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 155 | * and continues execution in postcar stage. */ |
| 156 | void platform_enter_postcar(void) |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 157 | { |
| 158 | struct postcar_frame pcf; |
| 159 | uintptr_t top_of_ram; |
| 160 | |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 161 | if (postcar_frame_init(&pcf, 0)) |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 162 | die("Unable to initialize postcar frame.\n"); |
| 163 | |
| 164 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 165 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 166 | |
| 167 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 168 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 169 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 170 | /* Cache 8 MiB region below the top of ram and 2 MiB above top of |
| 171 | * ram to cover both cbmem as the TSEG region. |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 172 | */ |
| 173 | top_of_ram = (uintptr_t)cbmem_top(); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 174 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, |
| 175 | MTRR_TYPE_WRBACK); |
| 176 | postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), |
| 177 | northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 178 | |
Arthur Heymans | aa7cf55 | 2018-06-03 10:44:55 +0200 | [diff] [blame] | 179 | run_postcar_phase(&pcf); |
| 180 | |
| 181 | /* We do not return here. */ |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 182 | } |