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review.coreboot.org / coreboot / fb2b584ac4ccb2030ab9e111ee44de196270b27a / . / util / msrtool / geodegx2.c
blob: ae5d887c2d1205bcd5bb45a77f85a41d538e22be [file] [log] [blame]
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]1/*
2 * This file is part of msrtool.
3 *
4 * Copyright (c) 2008 Peter Stuge <peter@stuge.se>
5 * Copyright (c) 2009 Nils Jacobs <njacobs8@hetnet.nl>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include "msrtool.h"
22
23int geodegx2_probe(const struct targetdef *target) {
24 struct cpuid_t *id = cpuid();
25 return 5 == id->family && 5 == id->model;
26}
27
28const struct msrdef geodegx2_msrs[] = {
Nils Jacobsfb2b5842011-01-19 06:56:33 +0000[diff] [blame^]29 { 0x10000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM0", "GLIU0 P2D Base Mask Descriptor 0", {
30 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
31 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
32 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
33 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
34 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
35 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
36 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
37 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
38 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
39 { BITVAL_EOT }
40 }},
41 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
42 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
43 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
44 { BITVAL_EOT }
45 }},
46 { 59, 20, RESERVED },
47 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
48 { BITVAL_EOT }
49 }},
50 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
51 { BITVAL_EOT }
52 }},
53 { BITS_EOT }
54 }},
55 { 0x10000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM1", "GLIU0 P2D Base Mask Descriptor 1", {
56 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
57 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
58 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
59 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
60 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
61 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
62 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
63 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
64 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
65 { BITVAL_EOT }
66 }},
67 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
68 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
69 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
70 { BITVAL_EOT }
71 }},
72 { 59, 20, RESERVED },
73 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
74 { BITVAL_EOT }
75 }},
76 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
77 { BITVAL_EOT }
78 }},
79 { BITS_EOT }
80 }},
81 { 0x10000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM2", "GLIU0 P2D Base Mask Descriptor 2", {
82 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
83 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
84 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
85 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
86 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
87 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
88 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
89 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
90 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
91 { BITVAL_EOT }
92 }},
93 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
94 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
95 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
96 { BITVAL_EOT }
97 }},
98 { 59, 20, RESERVED },
99 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
100 { BITVAL_EOT }
101 }},
102 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
103 { BITVAL_EOT }
104 }},
105 { BITS_EOT }
106 }},
107 { 0x10000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM3", "GLIU0 P2D Base Mask Descriptor 3", {
108 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
109 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
110 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
111 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
112 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
113 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
114 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
115 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
116 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
117 { BITVAL_EOT }
118 }},
119 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
120 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
121 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
122 { BITVAL_EOT }
123 }},
124 { 59, 20, RESERVED },
125 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
126 { BITVAL_EOT }
127 }},
128 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
129 { BITVAL_EOT }
130 }},
131 { BITS_EOT }
132 }},
133 { 0x10000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM4", "GLIU0 P2D Base Mask Descriptor 4", {
134 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
135 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
136 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
137 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
138 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
139 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
140 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
141 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
142 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
143 { BITVAL_EOT }
144 }},
145 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
146 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
147 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
148 { BITVAL_EOT }
149 }},
150 { 59, 20, RESERVED },
151 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
152 { BITVAL_EOT }
153 }},
154 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
155 { BITVAL_EOT }
156 }},
157 { BITS_EOT }
158 }},
159 { 0x10000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM5", "GLIU0 P2D Base Mask Descriptor 5", {
160 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
161 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
162 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
163 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
164 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
165 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
166 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
167 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
168 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
169 { BITVAL_EOT }
170 }},
171 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
172 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
173 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
174 { BITVAL_EOT }
175 }},
176 { 59, 20, RESERVED },
177 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
178 { BITVAL_EOT }
179 }},
180 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
181 { BITVAL_EOT }
182 }},
183 { BITS_EOT }
184 }},
185 { 0x10000026, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO0", "GLIU0 P2D Base Mask Offset Descriptor 0", {
186 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
187 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
188 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
189 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
190 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
191 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
192 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
193 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
194 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
195 { BITVAL_EOT }
196 }},
197 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
198 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
199 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
200 { BITVAL_EOT }
201 }},
202 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
203 { BITVAL_EOT }
204 }},
205 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
206 { BITVAL_EOT }
207 }},
208 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
209 { BITVAL_EOT }
210 }},
211 { BITS_EOT }
212 }},
213 { 0x10000027, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO1", "GLIU0 P2D Base Mask Offset Descriptor 1", {
214 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
215 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
216 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
217 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
218 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
219 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
220 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
221 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
222 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
223 { BITVAL_EOT }
224 }},
225 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
226 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
227 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
228 { BITVAL_EOT }
229 }},
230 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
231 { BITVAL_EOT }
232 }},
233 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
234 { BITVAL_EOT }
235 }},
236 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
237 { BITVAL_EOT }
238 }},
239 { BITS_EOT }
240 }},
241 { 0x10000028, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R0", "GLIU0 P2D Range Descriptor 0", {
242 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
243 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
244 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
245 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
246 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
247 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
248 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
249 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
250 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
251 { BITVAL_EOT }
252 }},
253 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
254 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
255 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
256 { BITVAL_EOT }
257 }},
258 { 59, 20, RESERVED },
259 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
260 { BITVAL_EOT }
261 }},
262 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
263 { BITVAL_EOT }
264 }},
265 { BITS_EOT }
266 }},
267 { 0x10000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO0", "GLIU0 P2D Range Offset Descriptor 0", {
268 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
269 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
270 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
271 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
272 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
273 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
274 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
275 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
276 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
277 { BITVAL_EOT }
278 }},
279 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
280 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
281 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
282 { BITVAL_EOT }
283 }},
284 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
285 { BITVAL_EOT }
286 }},
287 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
288 { BITVAL_EOT }
289 }},
290 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
291 { BITVAL_EOT }
292 }},
293 { BITS_EOT }
294 }},
295 { 0x1000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO1", "GLIU0 P2D Range Offset Descriptor 1", {
296 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
297 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
298 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
299 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
300 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
301 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
302 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
303 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
304 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
305 { BITVAL_EOT }
306 }},
307 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
308 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
309 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
310 { BITVAL_EOT }
311 }},
312 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
313 { BITVAL_EOT }
314 }},
315 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
316 { BITVAL_EOT }
317 }},
318 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
319 { BITVAL_EOT }
320 }},
321 { BITS_EOT }
322 }},
323 { 0x1000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO2", "GLIU0 P2D Range Offset Descriptor 2", {
324 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
325 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
326 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
327 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
328 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
329 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
330 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
331 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
332 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
333 { BITVAL_EOT }
334 }},
335 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
336 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
337 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
338 { BITVAL_EOT }
339 }},
340 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
341 { BITVAL_EOT }
342 }},
343 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
344 { BITVAL_EOT }
345 }},
346 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
347 { BITVAL_EOT }
348 }},
349 { BITS_EOT }
350 }},
351 { 0x1000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_P2D_SC0", "GLIU0 P2D Swiss Cheese Descriptor 0", {
352 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
353 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
354 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
355 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
356 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
357 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
358 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
359 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
360 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
361 { BITVAL_EOT }
362 }},
363 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
364 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
365 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
366 { BITVAL_EOT }
367 }},
368 { 59, 12, RESERVED },
369 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, {
370 { BITVAL_EOT }
371 }},
372 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, {
373 { BITVAL_EOT }
374 }},
375 { 15, 2, RESERVED },
376 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, {
377 { BITVAL_EOT }
378 }},
379 { BITS_EOT }
380 }},
381 { 0x100000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM0", "GLIU0 IOD Base Mask Descriptor 0", {
382 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
383 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
384 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
385 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
386 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
387 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
388 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
389 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
390 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
391 { BITVAL_EOT }
392 }},
393 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
394 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
395 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
396 { BITVAL_EOT }
397 }},
398 { 59, 20, RESERVED },
399 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
400 { BITVAL_EOT }
401 }},
402 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
403 { BITVAL_EOT }
404 }},
405 { BITS_EOT }
406 }},
407 { 0x100000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM1", "GLIU0 IOD Base Mask Descriptor 1", {
408 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
409 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
410 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
411 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
412 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
413 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
414 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
415 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
416 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
417 { BITVAL_EOT }
418 }},
419 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
420 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
421 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
422 { BITVAL_EOT }
423 }},
424 { 59, 20, RESERVED },
425 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
426 { BITVAL_EOT }
427 }},
428 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
429 { BITVAL_EOT }
430 }},
431 { BITS_EOT }
432 }},
433 { 0x100000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM2", "GLIU0 IOD Base Mask Descriptor 2", {
434 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
435 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
436 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
437 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
438 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
439 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
440 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
441 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
442 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
443 { BITVAL_EOT }
444 }},
445 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
446 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
447 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
448 { BITVAL_EOT }
449 }},
450 { 59, 20, RESERVED },
451 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
452 { BITVAL_EOT }
453 }},
454 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
455 { BITVAL_EOT }
456 }},
457 { BITS_EOT }
458 }},
459 { 0x100000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC0", "GLIU0 IOD Swiss Cheese Descriptor 0", {
460 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
461 { BITVAL_EOT }
462 }},
463 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
464 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
465 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
466 { BITVAL_EOT }
467 }},
468 { 59, 28, RESERVED },
469 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
470 { BITVAL_EOT }
471 }},
472 { 23, 2, RESERVED },
473 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
474 { BITVAL_EOT }
475 }},
476 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
477 { BITVAL_EOT }
478 }},
479 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
480 { BITVAL_EOT }
481 }},
482 { 2, 3, RESERVED },
483 { BITS_EOT }
484 }},
485 { 0x100000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC1", "GLIU0 IOD Swiss Cheese Descriptor 1", {
486 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
487 { BITVAL_EOT }
488 }},
489 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
490 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
491 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
492 { BITVAL_EOT }
493 }},
494 { 59, 28, RESERVED },
495 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
496 { BITVAL_EOT }
497 }},
498 { 23, 2, RESERVED },
499 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
500 { BITVAL_EOT }
501 }},
502 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
503 { BITVAL_EOT }
504 }},
505 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
506 { BITVAL_EOT }
507 }},
508 { 2, 3, RESERVED },
509 { BITS_EOT }
510 }},
511 { 0x100000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC2", "GLIU0 IOD Swiss Cheese Descriptor 2", {
512 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
513 { BITVAL_EOT }
514 }},
515 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
516 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
517 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
518 { BITVAL_EOT }
519 }},
520 { 59, 28, RESERVED },
521 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
522 { BITVAL_EOT }
523 }},
524 { 23, 2, RESERVED },
525 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
526 { BITVAL_EOT }
527 }},
528 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
529 { BITVAL_EOT }
530 }},
531 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
532 { BITVAL_EOT }
533 }},
534 { 2, 3, RESERVED },
535 { BITS_EOT }
536 }},
537 { 0x100000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC3", "GLIU0 IOD Swiss Cheese Descriptor 3", {
538 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
539 { BITVAL_EOT }
540 }},
541 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
542 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
543 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
544 { BITVAL_EOT }
545 }},
546 { 59, 28, RESERVED },
547 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
548 { BITVAL_EOT }
549 }},
550 { 23, 2, RESERVED },
551 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
552 { BITVAL_EOT }
553 }},
554 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
555 { BITVAL_EOT }
556 }},
557 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
558 { BITVAL_EOT }
559 }},
560 { 2, 3, RESERVED },
561 { BITS_EOT }
562 }},
563 { 0x100000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC4", "GLIU0 IOD Swiss Cheese Descriptor 4", {
564 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
565 { BITVAL_EOT }
566 }},
567 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
568 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
569 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
570 { BITVAL_EOT }
571 }},
572 { 59, 28, RESERVED },
573 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
574 { BITVAL_EOT }
575 }},
576 { 23, 2, RESERVED },
577 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
578 { BITVAL_EOT }
579 }},
580 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
581 { BITVAL_EOT }
582 }},
583 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
584 { BITVAL_EOT }
585 }},
586 { 2, 3, RESERVED },
587 { BITS_EOT }
588 }},
589 { 0x100000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC5", "GLIU0 IOD Swiss Cheese Descriptor 5", {
590 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
591 { BITVAL_EOT }
592 }},
593 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
594 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
595 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
596 { BITVAL_EOT }
597 }},
598 { 59, 28, RESERVED },
599 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
600 { BITVAL_EOT }
601 }},
602 { 23, 2, RESERVED },
603 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
604 { BITVAL_EOT }
605 }},
606 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
607 { BITVAL_EOT }
608 }},
609 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
610 { BITVAL_EOT }
611 }},
612 { 2, 3, RESERVED },
613 { BITS_EOT }
614 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]615 { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
616 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
617 { MSR1(0), "Reserved" },
618 { MSR1(1), "8 MB" },
619 { MSR1(2), "16 MB" },
620 { MSR1(3), "32 MB" },
621 { MSR1(4), "64 MB" },
622 { MSR1(5), "128 MB" },
623 { MSR1(6), "256 MB" },
624 { MSR1(7), "512 MB" },
625 { MSR1(8), "Reserved" },
626 { MSR1(9), "Reserved" },
627 { MSR1(10), "Reserved" },
628 { MSR1(11), "Reserved" },
629 { MSR1(12), "Reserved" },
630 { MSR1(13), "Reserved" },
631 { MSR1(14), "Reserved" },
632 { MSR1(15), "Reserved" },
633 { BITVAL_EOT }
634 }},
635 { 59, 3, RESERVED },
636 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
637 { MSR1(0), "1 Module bank" },
638 { MSR1(1), "2 Module banks" },
639 { BITVAL_EOT }
640 }},
641 { 55, 3, RESERVED },
642 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
643 { MSR1(0), "2 Component banks" },
644 { MSR1(1), "4 Component banks" },
645 { BITVAL_EOT }
646 }},
647 { 51, 1, RESERVED },
648 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
649 { MSR1(0), "1 KB" },
650 { MSR1(1), "2 KB" },
651 { MSR1(2), "4 KB" },
652 { MSR1(3), "8 KB" },
653 { MSR1(4), "16 KB" },
654 { MSR1(5), "Reserved" },
655 { MSR1(6), "Reserved" },
656 { MSR1(7), "DIMM1 Not Installed" },
657 { BITVAL_EOT }
658 }},
659 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
660 { MSR1(0), "Reserved" },
661 { MSR1(1), "8 MB" },
662 { MSR1(2), "16 MB" },
663 { MSR1(3), "32 MB" },
664 { MSR1(4), "64 MB" },
665 { MSR1(5), "128 MB" },
666 { MSR1(6), "256 MB" },
667 { MSR1(7), "512 MB" },
668 { MSR1(8), "Reserved" },
669 { MSR1(9), "Reserved" },
670 { MSR1(10), "Reserved" },
671 { MSR1(11), "Reserved" },
672 { MSR1(12), "Reserved" },
673 { MSR1(13), "Reserved" },
674 { MSR1(14), "Reserved" },
675 { MSR1(15), "Reserved" },
676 { BITVAL_EOT }
677 }},
678 { 43, 3, RESERVED },
679 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
680 { MSR1(0), "1 Module bank" },
681 { MSR1(1), "2 Module banks" },
682 { BITVAL_EOT }
683 }},
684 { 39, 3, RESERVED },
685 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
686 { MSR1(0), "2 Component banks" },
687 { MSR1(1), "4 Component banks" },
688 { BITVAL_EOT }
689 }},
690 { 35, 1, RESERVED },
691 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
692 { MSR1(0), "1 KB" },
693 { MSR1(1), "2 KB" },
694 { MSR1(2), "4 KB" },
695 { MSR1(3), "8 KB" },
696 { MSR1(4), "16 KB" },
697 { MSR1(5), "Reserved" },
698 { MSR1(6), "Reserved" },
699 { MSR1(7), "DIMM0 Not Installed" },
700 { BITVAL_EOT }
701 }},
702 { 31, 2, RESERVED },
703 { 29, 2, "EMR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
704 { MSR1(0), "Program the DIMM Mode Register" },
705 { MSR1(1), "Program the DIMM Extended Mode Register" },
706 { MSR1(2), "Reserved" },
707 { MSR1(3), "Reserved" },
708 { BITVAL_EOT }
709 }},
710 { 27, 1, RESERVED },
711 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
712 { MSR1(0), "Enable" },
713 { MSR1(1), "Disable" },
714 { BITVAL_EOT }
715 }},
716 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
717 { MSR1(0), "Normal" },
718 { MSR1(1), "Reduced" },
719 { BITVAL_EOT }
720 }},
721 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
722 { MSR1(0), "Enable" },
723 { MSR1(1), "Disable" },
724 { BITVAL_EOT }
725 }},
726 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
727 { 7, 2, "REF_STAG", "Refresh Staggering", PRESENT_DEC, {
728 { MSR1(0), "4 SDRAM Clks" },
729 { MSR1(1), "1 SDRAM Clks" },
730 { MSR1(2), "2 SDRAM Clks" },
731 { MSR1(3), "3 SDRAM Clks" },
732 { BITVAL_EOT }
733 }},
734 { 5, 2, RESERVED },
735 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
736 { 2, 1, RESERVED },
737 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
738 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
739 { BITS_EOT }
740 }},
741 { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
742 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
743 { 55, 3, RESERVED },
744 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
745 { MSR1(0), "ADDR[18]" },
746 { MSR1(1), "ADDR[19]" },
747 { MSR1(2), "ADDR[20]" },
748 { MSR1(3), "ADDR[21]" },
749 { BITVAL_EOT }
750 }},
751 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
752 { MSR1(0), "Disabled" },
753 { MSR1(1), "Enabled" },
754 { BITVAL_EOT }
755 }},
756 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
757 { MSR1(0), "Disabled" },
758 { MSR1(1), "Enabled" },
759 { BITVAL_EOT }
760 }},
761 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
762 { MSR1(0), "Disabled" },
763 { MSR1(1), "Enabled" },
764 { BITVAL_EOT }
765 }},
766 { 47, 8, RESERVED },
767 { 39, 1, "AP_B2B", "Autoprecharge Back-to-Back Command", PRESENT_BIN, {
768 { MSR1(0), "Enable" },
769 { MSR1(1), "Disable" },
770 { BITVAL_EOT }
771 }},
772 { 38, 1, "AP_EN", "Autoprecharge", PRESENT_BIN, {
773 { MSR1(0), "Enable" },
774 { MSR1(1), "Disable" },
775 { BITVAL_EOT }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]776 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]777 { 37, 4, RESERVED },
778 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
779 { MSR1(0), "Low Order Interleave" },
780 { MSR1(1), "High Order Interleave" },
781 { BITVAL_EOT }
782 }},
783 { 32, 1, RESERVED },
784 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
785 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
786 { MSR1(0), "Reserved" },
787 { MSR1(1), "Reserved" },
788 { MSR1(2), "2 Clks" },
789 { MSR1(3), "Reserved" },
790 { MSR1(4), "Reserved" },
791 { MSR1(5), "1.5 Clks" },
792 { MSR1(6), "2.5 Clks" },
793 { MSR1(7), "Reserved" },
794 { BITVAL_EOT }
795 }},
796 { 27, 4, "REF2ACT", "ACT to ACT/REF Period. tRC", PRESENT_BIN, {
797 { MSR1(0), "Reserved" },
798 { MSR1(1), "1 Clks" },
799 { MSR1(2), "2 Clks" },
800 { MSR1(3), "3 Clks" },
801 { MSR1(4), "4 Clks" },
802 { MSR1(5), "5 Clks" },
803 { MSR1(6), "7 Clks" },
804 { MSR1(7), "8 Clks" },
805 { MSR1(8), "9 Clks" },
806 { MSR1(9), "10 Clks" },
807 { MSR1(10), "11 Clks" },
808 { MSR1(11), "12 Clks" },
809 { MSR1(12), "13 Clks" },
810 { MSR1(13), "14 Clks" },
811 { MSR1(14), "15 Clks" },
812 { MSR1(15), "16 Clks" },
813 { BITVAL_EOT }
814 }},
815 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_BIN, {
816 { MSR1(0), "Reserved" },
817 { MSR1(1), "1 Clks" },
818 { MSR1(2), "2 Clks" },
819 { MSR1(3), "3 Clks" },
820 { MSR1(4), "4 Clks" },
821 { MSR1(5), "5 Clks" },
822 { MSR1(6), "7 Clks" },
823 { MSR1(7), "8 Clks" },
824 { MSR1(8), "9 Clks" },
825 { MSR1(9), "10 Clks" },
826 { MSR1(10), "11 Clks" },
827 { MSR1(11), "12 Clks" },
828 { MSR1(12), "13 Clks" },
829 { MSR1(13), "14 Clks" },
830 { MSR1(14), "15 Clks" },
831 { MSR1(15), "16 Clks" },
832 { BITVAL_EOT }
833 }},
834 { 19, 1, RESERVED },
835 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_BIN, {
836 { MSR1(0), "Reserved" },
837 { MSR1(1), "1 Clks" },
838 { MSR1(2), "2 Clks" },
839 { MSR1(3), "3 Clks" },
840 { MSR1(4), "4 Clks" },
841 { MSR1(5), "5 Clks" },
842 { MSR1(6), "6 Clks" },
843 { MSR1(7), "7 Clks" },
844 { BITVAL_EOT }
845 }},
846 { 15, 1, RESERVED },
847 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_BIN, {
848 { MSR1(0), "Reserved" },
849 { MSR1(1), "1 Clks" },
850 { MSR1(2), "2 Clks" },
851 { MSR1(3), "3 Clks" },
852 { MSR1(4), "4 Clks" },
853 { MSR1(5), "5 Clks" },
854 { MSR1(6), "6 Clks" },
855 { MSR1(7), "Reserved" },
856 { BITVAL_EOT }
857 }},
858 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_BIN, {
859 { MSR1(0), "Reserved" },
860 { MSR1(1), "1 Clks" },
861 { MSR1(2), "2 Clks" },
862 { MSR1(3), "3 Clks" },
863 { MSR1(4), "4 Clks" },
864 { MSR1(5), "5 Clks" },
865 { MSR1(6), "6 Clks" },
866 { MSR1(7), "7 Clks" },
867 { MSR1(8), "Reserved" },
868 { MSR1(9), "Reserved" },
869 { MSR1(10), "Reserved" },
870 { MSR1(11), "Reserved" },
871 { MSR1(12), "Reserved" },
872 { MSR1(13), "Reserved" },
873 { MSR1(14), "Reserved" },
874 { MSR1(15), "Reserved" },
875 { BITVAL_EOT }
876 }},
877 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
878 { MSR1(0), "Invalid value" },
879 { MSR1(1), "1 Clks" },
880 { MSR1(2), "2 Clks" },
881 { MSR1(3), "3 Clks" },
882 { BITVAL_EOT }
883 }},
884 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
885 { MSR1(0), "Invalid value" },
886 { MSR1(1), "1 Clks" },
887 { MSR1(2), "2 Clks" },
888 { MSR1(3), "3 Clks" },
889 { BITVAL_EOT }
890 }},
891 { 3, 1, RESERVED },
892 { 2, 3, "DAL", "Data-in to ACT (REF) Period. tDAL", PRESENT_BIN, {
893 { MSR1(0), "Reserved" },
894 { MSR1(1), "1 clks" },
895 { MSR1(2), "2 Clks" },
896 { MSR1(3), "3 Clks" },
897 { MSR1(4), "4 Clks" },
898 { MSR1(5), "5 Clks" },
899 { MSR1(6), "6 Clks" },
900 { MSR1(7), "7 Clks" },
901 { BITVAL_EOT }
902 }},
903 { BITS_EOT }
904 }},
905 { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0), "MC_CF1017_DATA", "Feature Enables", {
906 { 63, 55, RESERVED },
907 { 8, 1, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, {
908 { MSR1(0), "No delay" },
909 { MSR1(1), "Enable delay" },
910 { BITVAL_EOT }
911 }},
912 { 7, 5, RESERVED },
913 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
914 { MSR1(0), "Reserved" },
915 { MSR1(1), "Value when unbuffered DDR SDRAMs are used" },
916 { MSR1(2), "Value when registered DDR SDRAMs are used" },
917 { MSR1(3), "Reserved" },
918 { BITVAL_EOT }
919 }},
920 { BITS_EOT }
921 }},
922 { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
923 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
924 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
925 { BITS_EOT }
926 }},
927 { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
928 { 63, 28, RESERVED },
929 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, {
930 { MSR1(0), "Counter 1 counts" },
931 { MSR1(1), "Stop Counter" },
932 { BITVAL_EOT }
933 }},
934 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, {
935 { MSR1(0), "Do nothing" },
936 { MSR1(1), "Reset counter 1" },
937 { BITVAL_EOT }
938 }},
939 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, {
940 { MSR1(0), "Counter 0 counts" },
941 { MSR1(1), "Stop counter 0" },
942 { BITVAL_EOT }
943 }},
944 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, {
945 { MSR1(0), "Do nothing" },
946 { MSR1(1), "Reset counter 0" },
947 { BITVAL_EOT }
948 }},
949 { 31, 8, "CNT1_MASK", "Counter 1 Mask", PRESENT_BIN, NOBITS },
950 { 23, 8, "CNT1_DATA", "Counter 1 Data", PRESENT_BIN, NOBITS },
951 { 15, 8, "CNT0_MASK", "Counter 0 Mask", PRESENT_BIN, NOBITS },
952 { 7, 8, "CNT0_DATA", "Counter 0 Data", PRESENT_BIN, NOBITS },
953 { BITS_EOT }
954 }},
955 { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x300), "MC_CFCLK_DBUG", "Clocking and Debug", {
956 { 63, 29, RESERVED },
957 { 34, 1, "B2B_EN", "Back-to-Back Command Enable", PRESENT_BIN, {
958 { MSR1(0), "Allow back-to-back commands" },
959 { MSR1(1), "Disable back-to-back commands" },
960 { BITVAL_EOT }
961 }},
962 { 33, 1, RESERVED },
963 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
964 { MSR1(0), "Disable" },
965 { MSR1(1), "Enable" },
966 { BITVAL_EOT }
967 }},
968 { 31, 22, RESERVED },
969 { 9, 1, "MASK_CKE[1:0]", "CKE Mask", PRESENT_BIN, {
970 { MSR1(0), "CKE1 output enable unmasked" },
971 { MSR1(1), "CKE1 output enable masked" },
972 { BITVAL_EOT }
973 }},
974 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
975 { MSR1(0), "CKE0 output enable unmasked" },
976 { MSR1(1), "CKE0 output enable masked" },
977 { BITVAL_EOT }
978 }},
979 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
980 { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
981 { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
982 { BITVAL_EOT }
983 }},
984 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
985 { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
986 { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
987 { BITVAL_EOT }
988 }},
989 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
990 { MSR1(0), "MA and BA output enable unmasked" },
991 { MSR1(1), "MA and BA output enable masked" },
992 { BITVAL_EOT }
993 }},
994 { 4, 5, RESERVED },
995 { BITS_EOT }
996 }},
Nils Jacobsfb2b5842011-01-19 06:56:33 +0000[diff] [blame^]997 { 0x40000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM0", "GLIU1 P2D Base Mask Descriptor 0", {
998 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
999 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1000 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1001 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1002 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1003 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1004 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1005 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1006 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1007 { BITVAL_EOT }
1008 }},
1009 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1010 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1011 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1012 { BITVAL_EOT }
1013 }},
1014 { 59, 20, RESERVED },
1015 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1016 { BITVAL_EOT }
1017 }},
1018 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1019 { BITVAL_EOT }
1020 }},
1021 { BITS_EOT }
1022 }},
1023 { 0x40000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM1", "GLIU1 P2D Base Mask Descriptor 1", {
1024 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1025 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1026 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1027 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1028 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1029 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1030 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1031 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1032 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1033 { BITVAL_EOT }
1034 }},
1035 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1036 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1037 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1038 { BITVAL_EOT }
1039 }},
1040 { 59, 20, RESERVED },
1041 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1042 { BITVAL_EOT }
1043 }},
1044 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1045 { BITVAL_EOT }
1046 }},
1047 { BITS_EOT }
1048 }},
1049 { 0x40000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM2", "GLIU1 P2D Base Mask Descriptor 2", {
1050 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1051 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1052 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1053 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1054 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1055 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1056 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1057 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1058 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1059 { BITVAL_EOT }
1060 }},
1061 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1062 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1063 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1064 { BITVAL_EOT }
1065 }},
1066 { 59, 20, RESERVED },
1067 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1068 { BITVAL_EOT }
1069 }},
1070 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1071 { BITVAL_EOT }
1072 }},
1073 { BITS_EOT }
1074 }},
1075 { 0x40000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM3", "GLIU1 P2D Base Mask Descriptor 3", {
1076 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1077 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1078 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1079 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1080 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1081 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1082 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1083 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1084 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1085 { BITVAL_EOT }
1086 }},
1087 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1088 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1089 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1090 { BITVAL_EOT }
1091 }},
1092 { 59, 20, RESERVED },
1093 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1094 { BITVAL_EOT }
1095 }},
1096 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1097 { BITVAL_EOT }
1098 }},
1099 { BITS_EOT }
1100 }},
1101 { 0x40000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM4", "GLIU1 P2D Base Mask Descriptor 4", {
1102 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1103 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1104 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1105 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1106 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1107 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1108 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1109 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1110 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1111 { BITVAL_EOT }
1112 }},
1113 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1114 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1115 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1116 { BITVAL_EOT }
1117 }},
1118 { 59, 20, RESERVED },
1119 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1120 { BITVAL_EOT }
1121 }},
1122 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1123 { BITVAL_EOT }
1124 }},
1125 { BITS_EOT }
1126 }},
1127 { 0x40000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM5", "GLIU1 P2D Base Mask Descriptor 5", {
1128 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1129 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1130 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1131 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1132 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1133 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1134 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1135 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1136 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1137 { BITVAL_EOT }
1138 }},
1139 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1140 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1141 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1142 { BITVAL_EOT }
1143 }},
1144 { 59, 20, RESERVED },
1145 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1146 { BITVAL_EOT }
1147 }},
1148 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1149 { BITVAL_EOT }
1150 }},
1151 { BITS_EOT }
1152 }},
1153 { 0x40000026, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM6", "GLIU1 P2D Base Mask Descriptor 6", {
1154 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1155 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1156 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1157 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1158 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1159 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1160 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1161 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1162 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1163 { BITVAL_EOT }
1164 }},
1165 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1166 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1167 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1168 { BITVAL_EOT }
1169 }},
1170 { 59, 20, RESERVED },
1171 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1172 { BITVAL_EOT }
1173 }},
1174 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1175 { BITVAL_EOT }
1176 }},
1177 { BITS_EOT }
1178 }},
1179 { 0x40000027, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM7", "GLIU1 P2D Base Mask Descriptor 7", {
1180 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1181 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1182 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1183 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1184 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1185 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1186 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1187 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1188 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1189 { BITVAL_EOT }
1190 }},
1191 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1192 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1193 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1194 { BITVAL_EOT }
1195 }},
1196 { 59, 20, RESERVED },
1197 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1198 { BITVAL_EOT }
1199 }},
1200 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1201 { BITVAL_EOT }
1202 }},
1203 { BITS_EOT }
1204 }},
1205 { 0x40000028, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM8", "GLIU1 P2D Base Mask Descriptor 8", {
1206 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1207 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1208 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1209 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1210 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1211 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1212 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1213 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1214 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1215 { BITVAL_EOT }
1216 }},
1217 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1218 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1219 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1220 { BITVAL_EOT }
1221 }},
1222 { 59, 20, RESERVED },
1223 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1224 { BITVAL_EOT }
1225 }},
1226 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1227 { BITVAL_EOT }
1228 }},
1229 { BITS_EOT }
1230 }},
1231 { 0x40000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R0", "GLIU0 P2D Range Descriptor 0", {
1232 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1233 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1234 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1235 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1236 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1237 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1238 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1239 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1240 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1241 { BITVAL_EOT }
1242 }},
1243 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1244 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1245 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1246 { BITVAL_EOT }
1247 }},
1248 { 59, 20, RESERVED },
1249 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1250 { BITVAL_EOT }
1251 }},
1252 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1253 { BITVAL_EOT }
1254 }},
1255 { BITS_EOT }
1256 }},
1257 { 0x4000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R1", "GLIU0 P2D Range Descriptor 1", {
1258 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1259 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1260 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1261 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1262 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1263 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1264 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1265 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1266 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1267 { BITVAL_EOT }
1268 }},
1269 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1270 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1271 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1272 { BITVAL_EOT }
1273 }},
1274 { 59, 20, RESERVED },
1275 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1276 { BITVAL_EOT }
1277 }},
1278 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1279 { BITVAL_EOT }
1280 }},
1281 { BITS_EOT }
1282 }},
1283 { 0x4000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R2", "GLIU0 P2D Range Descriptor 2", {
1284 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1285 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1286 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1287 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1288 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1289 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1290 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1291 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1292 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1293 { BITVAL_EOT }
1294 }},
1295 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1296 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1297 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1298 { BITVAL_EOT }
1299 }},
1300 { 59, 20, RESERVED },
1301 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1302 { BITVAL_EOT }
1303 }},
1304 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1305 { BITVAL_EOT }
1306 }},
1307 { BITS_EOT }
1308 }},
1309 { 0x4000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R3", "GLIU0 P2D Range Descriptor 3", {
1310 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1311 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1312 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1313 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1314 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1315 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1316 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1317 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1318 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1319 { BITVAL_EOT }
1320 }},
1321 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1322 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1323 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1324 { BITVAL_EOT }
1325 }},
1326 { 59, 20, RESERVED },
1327 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1328 { BITVAL_EOT }
1329 }},
1330 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1331 { BITVAL_EOT }
1332 }},
1333 { BITS_EOT }
1334 }},
1335 { 0x4000002D, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_P2D_SC0", "GLIU1 P2D Swiss Cheese Descriptor 0", {
1336 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1337 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1338 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1339 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1340 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1341 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1342 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1343 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1344 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1345 { BITVAL_EOT }
1346 }},
1347 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1348 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1349 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1350 { BITVAL_EOT }
1351 }},
1352 { 59, 12, RESERVED },
1353 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, {
1354 { BITVAL_EOT }
1355 }},
1356 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, {
1357 { BITVAL_EOT }
1358 }},
1359 { 15, 2, RESERVED },
1360 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, {
1361 { BITVAL_EOT }
1362 }},
1363 { BITS_EOT }
1364 }},
1365 { 0x400000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM0", "GLIU1 IOD Base Mask Descriptor 0", {
1366 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1367 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1368 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1369 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1370 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1371 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1372 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1373 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1374 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1375 { BITVAL_EOT }
1376 }},
1377 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1378 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1379 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1380 { BITVAL_EOT }
1381 }},
1382 { 59, 20, RESERVED },
1383 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1384 { BITVAL_EOT }
1385 }},
1386 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1387 { BITVAL_EOT }
1388 }},
1389 { BITS_EOT }
1390 }},
1391 { 0x400000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM1", "GLIU1 IOD Base Mask Descriptor 1", {
1392 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1393 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1394 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1395 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1396 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1397 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1398 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1399 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1400 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1401 { BITVAL_EOT }
1402 }},
1403 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1404 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1405 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1406 { BITVAL_EOT }
1407 }},
1408 { 59, 20, RESERVED },
1409 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1410 { BITVAL_EOT }
1411 }},
1412 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1413 { BITVAL_EOT }
1414 }},
1415 { BITS_EOT }
1416 }},
1417 { 0x400000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM2", "GLIU1 IOD Base Mask Descriptor 2", {
1418 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1419 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1420 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1421 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1422 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1423 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1424 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1425 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1426 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1427 { BITVAL_EOT }
1428 }},
1429 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1430 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1431 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1432 { BITVAL_EOT }
1433 }},
1434 { 59, 20, RESERVED },
1435 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1436 { BITVAL_EOT }
1437 }},
1438 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1439 { BITVAL_EOT }
1440 }},
1441 { BITS_EOT }
1442 }},
1443 { 0x400000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC0", "GLIU1 IOD Swiss Cheese Descriptor 0", {
1444 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1445 { BITVAL_EOT }
1446 }},
1447 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1448 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1449 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1450 { BITVAL_EOT }
1451 }},
1452 { 59, 28, RESERVED },
1453 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1454 { BITVAL_EOT }
1455 }},
1456 { 23, 2, RESERVED },
1457 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1458 { BITVAL_EOT }
1459 }},
1460 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1461 { BITVAL_EOT }
1462 }},
1463 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1464 { BITVAL_EOT }
1465 }},
1466 { 2, 3, RESERVED },
1467 { BITS_EOT }
1468 }},
1469 { 0x400000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC1", "GLIU1 IOD Swiss Cheese Descriptor 1", {
1470 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1471 { BITVAL_EOT }
1472 }},
1473 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1474 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1475 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1476 { BITVAL_EOT }
1477 }},
1478 { 59, 28, RESERVED },
1479 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1480 { BITVAL_EOT }
1481 }},
1482 { 23, 2, RESERVED },
1483 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1484 { BITVAL_EOT }
1485 }},
1486 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1487 { BITVAL_EOT }
1488 }},
1489 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1490 { BITVAL_EOT }
1491 }},
1492 { 2, 3, RESERVED },
1493 { BITS_EOT }
1494 }},
1495 { 0x400000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC2", "GLIU1 IOD Swiss Cheese Descriptor 2", {
1496 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1497 { BITVAL_EOT }
1498 }},
1499 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1500 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1501 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1502 { BITVAL_EOT }
1503 }},
1504 { 59, 28, RESERVED },
1505 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1506 { BITVAL_EOT }
1507 }},
1508 { 23, 2, RESERVED },
1509 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1510 { BITVAL_EOT }
1511 }},
1512 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1513 { BITVAL_EOT }
1514 }},
1515 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1516 { BITVAL_EOT }
1517 }},
1518 { 2, 3, RESERVED },
1519 { BITS_EOT }
1520 }},
1521 { 0x400000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC3", "GLIU1 IOD Swiss Cheese Descriptor 3", {
1522 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1523 { BITVAL_EOT }
1524 }},
1525 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1526 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1527 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1528 { BITVAL_EOT }
1529 }},
1530 { 59, 28, RESERVED },
1531 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1532 { BITVAL_EOT }
1533 }},
1534 { 23, 2, RESERVED },
1535 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1536 { BITVAL_EOT }
1537 }},
1538 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1539 { BITVAL_EOT }
1540 }},
1541 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1542 { BITVAL_EOT }
1543 }},
1544 { 2, 3, RESERVED },
1545 { BITS_EOT }
1546 }},
1547 { 0x400000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC4", "GLIU1 IOD Swiss Cheese Descriptor 4", {
1548 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1549 { BITVAL_EOT }
1550 }},
1551 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1552 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1553 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1554 { BITVAL_EOT }
1555 }},
1556 { 59, 28, RESERVED },
1557 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1558 { BITVAL_EOT }
1559 }},
1560 { 23, 2, RESERVED },
1561 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1562 { BITVAL_EOT }
1563 }},
1564 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1565 { BITVAL_EOT }
1566 }},
1567 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1568 { BITVAL_EOT }
1569 }},
1570 { 2, 3, RESERVED },
1571 { BITS_EOT }
1572 }},
1573 { 0x400000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC5", "GLIU1 IOD Swiss Cheese Descriptor 5", {
1574 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1575 { BITVAL_EOT }
1576 }},
1577 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1578 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1579 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1580 { BITVAL_EOT }
1581 }},
1582 { 59, 28, RESERVED },
1583 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1584 { BITVAL_EOT }
1585 }},
1586 { 23, 2, RESERVED },
1587 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1588 { BITVAL_EOT }
1589 }},
1590 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1591 { BITVAL_EOT }
1592 }},
1593 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1594 { BITVAL_EOT }
1595 }},
1596 { 2, 3, RESERVED },
1597 { BITS_EOT }
1598 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]1599 { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
1600 { 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, {
1601 { MSR1(0), "Use default values" },
1602 { MSR1(1), "Use value in bits [62:0]" },
1603 { BITVAL_EOT }
1604 }},
1605 { 62, 2, RESERVED },
1606 { 60, 5, "GIO", "Delay Geode Companion Device", PRESENT_DEC, NOBITS },
1607 { 55, 5, "PCI_IN", "Delay PCI Inputs", PRESENT_DEC, NOBITS },
1608 { 50, 5, "PCI_OUT", "Delay PCI Outputs", PRESENT_DEC, NOBITS },
1609 { 45, 5, RESERVED},
1610 { 40, 5, "DOTCLK", "Delay Dot Clock", PRESENT_DEC, NOBITS },
1611 { 35, 5, "DRGB", "Delay Digital RGBs", PRESENT_DEC, NOBITS },
1612 { 30, 5, "SDCLK_IN", "Delay SDRAM Clock Input", PRESENT_DEC, NOBITS },
1613 { 25, 5, "SDCLK_OUT", "Delay SDRAM Clock Output", PRESENT_DEC, NOBITS },
1614 { 20, 5, "MEM_CTL", "Delay Memory Controls", PRESENT_DEC, NOBITS },
1615 { 15, 9, RESERVED},
1616 { 6, 1, "MEM_ODDOUT", "Delay Odd Memory Data Output Bits", PRESENT_DEC, {
1617 { MSR1(0), "No Delay" },
1618 { MSR1(1), "Delay" },
1619 { BITVAL_EOT }
1620 }},
1621 { 5, 2, RESERVED },
1622 { 3, 2, "DQS_CLK_IN", "Delay DQS Before Clocking Input", PRESENT_DEC, NOBITS },
1623 { 1, 2, "DQS_CLK_OUT", "Delay DQS Before Clocking Output", PRESENT_DEC, NOBITS },
1624 { BITS_EOT }
1625 }},
1626 { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
1627 { 63, 19, RESERVED },
1628 { 44, 4, "MDIV", "GLIU1 Divisor", PRESENT_BIN, {
1629 { MSR1(0), "Divide by 2" },
1630 { MSR1(1), "Divide by 3" },
1631 { MSR1(2), "Divide by 4" },
1632 { MSR1(3), "Divide by 5" },
1633 { MSR1(4), "Divide by 6" },
1634 { MSR1(5), "Divide by 7" },
1635 { MSR1(6), "Divide by 8" },
1636 { MSR1(7), "Divide by 9" },
1637 { MSR1(8), "Divide by 10" },
1638 { MSR1(9), "Divide by 11" },
1639 { MSR1(10), "Divide by 12" },
1640 { MSR1(11), "Divide by 13" },
1641 { MSR1(12), "Divide by 14" },
1642 { MSR1(13), "Divide by 15" },
1643 { MSR1(14), "Divide by 16" },
1644 { MSR1(15), "Divide by 17" },
1645 { BITVAL_EOT }
1646 }},
1647 { 40, 3, "VDIV", "CPU Core Divisor", PRESENT_BIN, {
1648 { MSR1(0), "Divide by 2" },
1649 { MSR1(1), "Divide by 3" },
1650 { MSR1(2), "Divide by 4" },
1651 { MSR1(3), "Divide by 5" },
1652 { MSR1(4), "Divide by 6" },
1653 { MSR1(5), "Divide by 7" },
1654 { MSR1(6), "Divide by 8" },
1655 { MSR1(7), "Divide by 9" },
1656 { BITVAL_EOT }
1657 }},
1658 { 37, 6, "FBDIV", "Feedback Devisor", PRESENT_DEC, NOBITS },
1659 { 31, 6, "SWFLAGS", "Software Flags", PRESENT_BIN, NOBITS },
1660 { 25, 1, "LOCK", "PLL Lock", PRESENT_DEC, {
1661 { MSR1(1), "PLL locked" },
1662 { MSR1(0), "PLL is not locked" },
1663 { BITVAL_EOT }
1664 }},
1665 { 24, 1, "LOCKWAIT", "Lock Wait", PRESENT_DEC, {
1666 { MSR1(0), "Disable" },
1667 { MSR1(1), "Enable" },
1668 { BITVAL_EOT }
1669 }},
1670 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
1671 { 15, 1, "BYPASS", "PLL Bypass", PRESENT_DEC, {
1672 { MSR1(0), "Use PLL as Clocksource" },
1673 { MSR1(1), "Use DOTREF as Clocksource" },
1674 { BITVAL_EOT }
1675 }},
1676 { 14, 1, "PD", "Power Down", PRESENT_DEC, {
1677 { MSR1(0), "PLL active" },
1678 { MSR1(1), "PLL in power down mode" },
1679 { BITVAL_EOT }
1680 }},
1681 { 13, 1, "RESETPLL", "PLL Reset", PRESENT_DEC, NOBITS },
1682 { 12, 2, RESERVED },
1683 { 10, 1, "DDRMODE", "DDR Mode", PRESENT_DEC, {
1684 { MSR1(0), "DDR communication enabled" },
1685 { MSR1(1), "Reserved" },
1686 { BITVAL_EOT }
1687 }},
1688 { 9, 1, "VA_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
1689 { MSR1(1), "CPU does not use GLIU1 FIFO" },
1690 { MSR1(0), "The GLIU1 FIFO is used by the CPU" },
1691 { BITVAL_EOT }
1692 }},
1693 { 8, 1, "PCI_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
1694 { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
1695 { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
1696 { BITVAL_EOT }
1697 }},
1698 { 7, 1, "DSTALL", "Debug Stall", PRESENT_DEC, NOBITS },
1699 { 6, 3, "BOOTSTRAP_STAT", "Bootstrap Status", PRESENT_BIN, NOBITS },
1700 { 3, 1, "DOTPOSTDIV3", "DOTPLL Post-Divide by 3", PRESENT_DEC, NOBITS },
1701 { 2, 1, "DOTPREMULT2", "DOTPLL Pre-Multiply by 2", PRESENT_DEC, NOBITS },
1702 { 1, 1, "DOTPREDIV2", "DOTPLL Pre-Divide by 2", PRESENT_DEC, NOBITS },
1703 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
1704 { BITS_EOT }
1705 }},
1706 { MSR_EOT }
1707};