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review.coreboot.org / coreboot / 7b0500c24ca103e8f8d802b476517afc2ac8eef5 / . / util / msrtool / geodegx2.c
blob: 8ec06c2172697c9993b1c01b1d8e113fdb2a263e [file] [log] [blame]
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]1/*
2 * This file is part of msrtool.
3 *
4 * Copyright (c) 2008 Peter Stuge <peter@stuge.se>
5 * Copyright (c) 2009 Nils Jacobs <njacobs8@hetnet.nl>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include "msrtool.h"
22
23int geodegx2_probe(const struct targetdef *target) {
24 struct cpuid_t *id = cpuid();
25 return 5 == id->family && 5 == id->model;
26}
27
28const struct msrdef geodegx2_msrs[] = {
29 { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
30 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
31 { MSR1(0), "Reserved" },
32 { MSR1(1), "8 MB" },
33 { MSR1(2), "16 MB" },
34 { MSR1(3), "32 MB" },
35 { MSR1(4), "64 MB" },
36 { MSR1(5), "128 MB" },
37 { MSR1(6), "256 MB" },
38 { MSR1(7), "512 MB" },
39 { MSR1(8), "Reserved" },
40 { MSR1(9), "Reserved" },
41 { MSR1(10), "Reserved" },
42 { MSR1(11), "Reserved" },
43 { MSR1(12), "Reserved" },
44 { MSR1(13), "Reserved" },
45 { MSR1(14), "Reserved" },
46 { MSR1(15), "Reserved" },
47 { BITVAL_EOT }
48 }},
49 { 59, 3, RESERVED },
50 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
51 { MSR1(0), "1 Module bank" },
52 { MSR1(1), "2 Module banks" },
53 { BITVAL_EOT }
54 }},
55 { 55, 3, RESERVED },
56 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
57 { MSR1(0), "2 Component banks" },
58 { MSR1(1), "4 Component banks" },
59 { BITVAL_EOT }
60 }},
61 { 51, 1, RESERVED },
62 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
63 { MSR1(0), "1 KB" },
64 { MSR1(1), "2 KB" },
65 { MSR1(2), "4 KB" },
66 { MSR1(3), "8 KB" },
67 { MSR1(4), "16 KB" },
68 { MSR1(5), "Reserved" },
69 { MSR1(6), "Reserved" },
70 { MSR1(7), "DIMM1 Not Installed" },
71 { BITVAL_EOT }
72 }},
73 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
74 { MSR1(0), "Reserved" },
75 { MSR1(1), "8 MB" },
76 { MSR1(2), "16 MB" },
77 { MSR1(3), "32 MB" },
78 { MSR1(4), "64 MB" },
79 { MSR1(5), "128 MB" },
80 { MSR1(6), "256 MB" },
81 { MSR1(7), "512 MB" },
82 { MSR1(8), "Reserved" },
83 { MSR1(9), "Reserved" },
84 { MSR1(10), "Reserved" },
85 { MSR1(11), "Reserved" },
86 { MSR1(12), "Reserved" },
87 { MSR1(13), "Reserved" },
88 { MSR1(14), "Reserved" },
89 { MSR1(15), "Reserved" },
90 { BITVAL_EOT }
91 }},
92 { 43, 3, RESERVED },
93 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
94 { MSR1(0), "1 Module bank" },
95 { MSR1(1), "2 Module banks" },
96 { BITVAL_EOT }
97 }},
98 { 39, 3, RESERVED },
99 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
100 { MSR1(0), "2 Component banks" },
101 { MSR1(1), "4 Component banks" },
102 { BITVAL_EOT }
103 }},
104 { 35, 1, RESERVED },
105 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
106 { MSR1(0), "1 KB" },
107 { MSR1(1), "2 KB" },
108 { MSR1(2), "4 KB" },
109 { MSR1(3), "8 KB" },
110 { MSR1(4), "16 KB" },
111 { MSR1(5), "Reserved" },
112 { MSR1(6), "Reserved" },
113 { MSR1(7), "DIMM0 Not Installed" },
114 { BITVAL_EOT }
115 }},
116 { 31, 2, RESERVED },
117 { 29, 2, "EMR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
118 { MSR1(0), "Program the DIMM Mode Register" },
119 { MSR1(1), "Program the DIMM Extended Mode Register" },
120 { MSR1(2), "Reserved" },
121 { MSR1(3), "Reserved" },
122 { BITVAL_EOT }
123 }},
124 { 27, 1, RESERVED },
125 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
126 { MSR1(0), "Enable" },
127 { MSR1(1), "Disable" },
128 { BITVAL_EOT }
129 }},
130 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
131 { MSR1(0), "Normal" },
132 { MSR1(1), "Reduced" },
133 { BITVAL_EOT }
134 }},
135 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
136 { MSR1(0), "Enable" },
137 { MSR1(1), "Disable" },
138 { BITVAL_EOT }
139 }},
140 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
141 { 7, 2, "REF_STAG", "Refresh Staggering", PRESENT_DEC, {
142 { MSR1(0), "4 SDRAM Clks" },
143 { MSR1(1), "1 SDRAM Clks" },
144 { MSR1(2), "2 SDRAM Clks" },
145 { MSR1(3), "3 SDRAM Clks" },
146 { BITVAL_EOT }
147 }},
148 { 5, 2, RESERVED },
149 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
150 { 2, 1, RESERVED },
151 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
152 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
153 { BITS_EOT }
154 }},
155 { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
156 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
157 { 55, 3, RESERVED },
158 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
159 { MSR1(0), "ADDR[18]" },
160 { MSR1(1), "ADDR[19]" },
161 { MSR1(2), "ADDR[20]" },
162 { MSR1(3), "ADDR[21]" },
163 { BITVAL_EOT }
164 }},
165 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
166 { MSR1(0), "Disabled" },
167 { MSR1(1), "Enabled" },
168 { BITVAL_EOT }
169 }},
170 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
171 { MSR1(0), "Disabled" },
172 { MSR1(1), "Enabled" },
173 { BITVAL_EOT }
174 }},
175 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
176 { MSR1(0), "Disabled" },
177 { MSR1(1), "Enabled" },
178 { BITVAL_EOT }
179 }},
180 { 47, 8, RESERVED },
181 { 39, 1, "AP_B2B", "Autoprecharge Back-to-Back Command", PRESENT_BIN, {
182 { MSR1(0), "Enable" },
183 { MSR1(1), "Disable" },
184 { BITVAL_EOT }
185 }},
186 { 38, 1, "AP_EN", "Autoprecharge", PRESENT_BIN, {
187 { MSR1(0), "Enable" },
188 { MSR1(1), "Disable" },
189 { BITVAL_EOT }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]190 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]191 { 37, 4, RESERVED },
192 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
193 { MSR1(0), "Low Order Interleave" },
194 { MSR1(1), "High Order Interleave" },
195 { BITVAL_EOT }
196 }},
197 { 32, 1, RESERVED },
198 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
199 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
200 { MSR1(0), "Reserved" },
201 { MSR1(1), "Reserved" },
202 { MSR1(2), "2 Clks" },
203 { MSR1(3), "Reserved" },
204 { MSR1(4), "Reserved" },
205 { MSR1(5), "1.5 Clks" },
206 { MSR1(6), "2.5 Clks" },
207 { MSR1(7), "Reserved" },
208 { BITVAL_EOT }
209 }},
210 { 27, 4, "REF2ACT", "ACT to ACT/REF Period. tRC", PRESENT_BIN, {
211 { MSR1(0), "Reserved" },
212 { MSR1(1), "1 Clks" },
213 { MSR1(2), "2 Clks" },
214 { MSR1(3), "3 Clks" },
215 { MSR1(4), "4 Clks" },
216 { MSR1(5), "5 Clks" },
217 { MSR1(6), "7 Clks" },
218 { MSR1(7), "8 Clks" },
219 { MSR1(8), "9 Clks" },
220 { MSR1(9), "10 Clks" },
221 { MSR1(10), "11 Clks" },
222 { MSR1(11), "12 Clks" },
223 { MSR1(12), "13 Clks" },
224 { MSR1(13), "14 Clks" },
225 { MSR1(14), "15 Clks" },
226 { MSR1(15), "16 Clks" },
227 { BITVAL_EOT }
228 }},
229 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_BIN, {
230 { MSR1(0), "Reserved" },
231 { MSR1(1), "1 Clks" },
232 { MSR1(2), "2 Clks" },
233 { MSR1(3), "3 Clks" },
234 { MSR1(4), "4 Clks" },
235 { MSR1(5), "5 Clks" },
236 { MSR1(6), "7 Clks" },
237 { MSR1(7), "8 Clks" },
238 { MSR1(8), "9 Clks" },
239 { MSR1(9), "10 Clks" },
240 { MSR1(10), "11 Clks" },
241 { MSR1(11), "12 Clks" },
242 { MSR1(12), "13 Clks" },
243 { MSR1(13), "14 Clks" },
244 { MSR1(14), "15 Clks" },
245 { MSR1(15), "16 Clks" },
246 { BITVAL_EOT }
247 }},
248 { 19, 1, RESERVED },
249 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_BIN, {
250 { MSR1(0), "Reserved" },
251 { MSR1(1), "1 Clks" },
252 { MSR1(2), "2 Clks" },
253 { MSR1(3), "3 Clks" },
254 { MSR1(4), "4 Clks" },
255 { MSR1(5), "5 Clks" },
256 { MSR1(6), "6 Clks" },
257 { MSR1(7), "7 Clks" },
258 { BITVAL_EOT }
259 }},
260 { 15, 1, RESERVED },
261 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_BIN, {
262 { MSR1(0), "Reserved" },
263 { MSR1(1), "1 Clks" },
264 { MSR1(2), "2 Clks" },
265 { MSR1(3), "3 Clks" },
266 { MSR1(4), "4 Clks" },
267 { MSR1(5), "5 Clks" },
268 { MSR1(6), "6 Clks" },
269 { MSR1(7), "Reserved" },
270 { BITVAL_EOT }
271 }},
272 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_BIN, {
273 { MSR1(0), "Reserved" },
274 { MSR1(1), "1 Clks" },
275 { MSR1(2), "2 Clks" },
276 { MSR1(3), "3 Clks" },
277 { MSR1(4), "4 Clks" },
278 { MSR1(5), "5 Clks" },
279 { MSR1(6), "6 Clks" },
280 { MSR1(7), "7 Clks" },
281 { MSR1(8), "Reserved" },
282 { MSR1(9), "Reserved" },
283 { MSR1(10), "Reserved" },
284 { MSR1(11), "Reserved" },
285 { MSR1(12), "Reserved" },
286 { MSR1(13), "Reserved" },
287 { MSR1(14), "Reserved" },
288 { MSR1(15), "Reserved" },
289 { BITVAL_EOT }
290 }},
291 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
292 { MSR1(0), "Invalid value" },
293 { MSR1(1), "1 Clks" },
294 { MSR1(2), "2 Clks" },
295 { MSR1(3), "3 Clks" },
296 { BITVAL_EOT }
297 }},
298 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
299 { MSR1(0), "Invalid value" },
300 { MSR1(1), "1 Clks" },
301 { MSR1(2), "2 Clks" },
302 { MSR1(3), "3 Clks" },
303 { BITVAL_EOT }
304 }},
305 { 3, 1, RESERVED },
306 { 2, 3, "DAL", "Data-in to ACT (REF) Period. tDAL", PRESENT_BIN, {
307 { MSR1(0), "Reserved" },
308 { MSR1(1), "1 clks" },
309 { MSR1(2), "2 Clks" },
310 { MSR1(3), "3 Clks" },
311 { MSR1(4), "4 Clks" },
312 { MSR1(5), "5 Clks" },
313 { MSR1(6), "6 Clks" },
314 { MSR1(7), "7 Clks" },
315 { BITVAL_EOT }
316 }},
317 { BITS_EOT }
318 }},
319 { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0), "MC_CF1017_DATA", "Feature Enables", {
320 { 63, 55, RESERVED },
321 { 8, 1, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, {
322 { MSR1(0), "No delay" },
323 { MSR1(1), "Enable delay" },
324 { BITVAL_EOT }
325 }},
326 { 7, 5, RESERVED },
327 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
328 { MSR1(0), "Reserved" },
329 { MSR1(1), "Value when unbuffered DDR SDRAMs are used" },
330 { MSR1(2), "Value when registered DDR SDRAMs are used" },
331 { MSR1(3), "Reserved" },
332 { BITVAL_EOT }
333 }},
334 { BITS_EOT }
335 }},
336 { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
337 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
338 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
339 { BITS_EOT }
340 }},
341 { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
342 { 63, 28, RESERVED },
343 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, {
344 { MSR1(0), "Counter 1 counts" },
345 { MSR1(1), "Stop Counter" },
346 { BITVAL_EOT }
347 }},
348 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, {
349 { MSR1(0), "Do nothing" },
350 { MSR1(1), "Reset counter 1" },
351 { BITVAL_EOT }
352 }},
353 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, {
354 { MSR1(0), "Counter 0 counts" },
355 { MSR1(1), "Stop counter 0" },
356 { BITVAL_EOT }
357 }},
358 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, {
359 { MSR1(0), "Do nothing" },
360 { MSR1(1), "Reset counter 0" },
361 { BITVAL_EOT }
362 }},
363 { 31, 8, "CNT1_MASK", "Counter 1 Mask", PRESENT_BIN, NOBITS },
364 { 23, 8, "CNT1_DATA", "Counter 1 Data", PRESENT_BIN, NOBITS },
365 { 15, 8, "CNT0_MASK", "Counter 0 Mask", PRESENT_BIN, NOBITS },
366 { 7, 8, "CNT0_DATA", "Counter 0 Data", PRESENT_BIN, NOBITS },
367 { BITS_EOT }
368 }},
369 { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x300), "MC_CFCLK_DBUG", "Clocking and Debug", {
370 { 63, 29, RESERVED },
371 { 34, 1, "B2B_EN", "Back-to-Back Command Enable", PRESENT_BIN, {
372 { MSR1(0), "Allow back-to-back commands" },
373 { MSR1(1), "Disable back-to-back commands" },
374 { BITVAL_EOT }
375 }},
376 { 33, 1, RESERVED },
377 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
378 { MSR1(0), "Disable" },
379 { MSR1(1), "Enable" },
380 { BITVAL_EOT }
381 }},
382 { 31, 22, RESERVED },
383 { 9, 1, "MASK_CKE[1:0]", "CKE Mask", PRESENT_BIN, {
384 { MSR1(0), "CKE1 output enable unmasked" },
385 { MSR1(1), "CKE1 output enable masked" },
386 { BITVAL_EOT }
387 }},
388 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
389 { MSR1(0), "CKE0 output enable unmasked" },
390 { MSR1(1), "CKE0 output enable masked" },
391 { BITVAL_EOT }
392 }},
393 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
394 { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
395 { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
396 { BITVAL_EOT }
397 }},
398 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
399 { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
400 { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
401 { BITVAL_EOT }
402 }},
403 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
404 { MSR1(0), "MA and BA output enable unmasked" },
405 { MSR1(1), "MA and BA output enable masked" },
406 { BITVAL_EOT }
407 }},
408 { 4, 5, RESERVED },
409 { BITS_EOT }
410 }},
411 { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
412 { 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, {
413 { MSR1(0), "Use default values" },
414 { MSR1(1), "Use value in bits [62:0]" },
415 { BITVAL_EOT }
416 }},
417 { 62, 2, RESERVED },
418 { 60, 5, "GIO", "Delay Geode Companion Device", PRESENT_DEC, NOBITS },
419 { 55, 5, "PCI_IN", "Delay PCI Inputs", PRESENT_DEC, NOBITS },
420 { 50, 5, "PCI_OUT", "Delay PCI Outputs", PRESENT_DEC, NOBITS },
421 { 45, 5, RESERVED},
422 { 40, 5, "DOTCLK", "Delay Dot Clock", PRESENT_DEC, NOBITS },
423 { 35, 5, "DRGB", "Delay Digital RGBs", PRESENT_DEC, NOBITS },
424 { 30, 5, "SDCLK_IN", "Delay SDRAM Clock Input", PRESENT_DEC, NOBITS },
425 { 25, 5, "SDCLK_OUT", "Delay SDRAM Clock Output", PRESENT_DEC, NOBITS },
426 { 20, 5, "MEM_CTL", "Delay Memory Controls", PRESENT_DEC, NOBITS },
427 { 15, 9, RESERVED},
428 { 6, 1, "MEM_ODDOUT", "Delay Odd Memory Data Output Bits", PRESENT_DEC, {
429 { MSR1(0), "No Delay" },
430 { MSR1(1), "Delay" },
431 { BITVAL_EOT }
432 }},
433 { 5, 2, RESERVED },
434 { 3, 2, "DQS_CLK_IN", "Delay DQS Before Clocking Input", PRESENT_DEC, NOBITS },
435 { 1, 2, "DQS_CLK_OUT", "Delay DQS Before Clocking Output", PRESENT_DEC, NOBITS },
436 { BITS_EOT }
437 }},
438 { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
439 { 63, 19, RESERVED },
440 { 44, 4, "MDIV", "GLIU1 Divisor", PRESENT_BIN, {
441 { MSR1(0), "Divide by 2" },
442 { MSR1(1), "Divide by 3" },
443 { MSR1(2), "Divide by 4" },
444 { MSR1(3), "Divide by 5" },
445 { MSR1(4), "Divide by 6" },
446 { MSR1(5), "Divide by 7" },
447 { MSR1(6), "Divide by 8" },
448 { MSR1(7), "Divide by 9" },
449 { MSR1(8), "Divide by 10" },
450 { MSR1(9), "Divide by 11" },
451 { MSR1(10), "Divide by 12" },
452 { MSR1(11), "Divide by 13" },
453 { MSR1(12), "Divide by 14" },
454 { MSR1(13), "Divide by 15" },
455 { MSR1(14), "Divide by 16" },
456 { MSR1(15), "Divide by 17" },
457 { BITVAL_EOT }
458 }},
459 { 40, 3, "VDIV", "CPU Core Divisor", PRESENT_BIN, {
460 { MSR1(0), "Divide by 2" },
461 { MSR1(1), "Divide by 3" },
462 { MSR1(2), "Divide by 4" },
463 { MSR1(3), "Divide by 5" },
464 { MSR1(4), "Divide by 6" },
465 { MSR1(5), "Divide by 7" },
466 { MSR1(6), "Divide by 8" },
467 { MSR1(7), "Divide by 9" },
468 { BITVAL_EOT }
469 }},
470 { 37, 6, "FBDIV", "Feedback Devisor", PRESENT_DEC, NOBITS },
471 { 31, 6, "SWFLAGS", "Software Flags", PRESENT_BIN, NOBITS },
472 { 25, 1, "LOCK", "PLL Lock", PRESENT_DEC, {
473 { MSR1(1), "PLL locked" },
474 { MSR1(0), "PLL is not locked" },
475 { BITVAL_EOT }
476 }},
477 { 24, 1, "LOCKWAIT", "Lock Wait", PRESENT_DEC, {
478 { MSR1(0), "Disable" },
479 { MSR1(1), "Enable" },
480 { BITVAL_EOT }
481 }},
482 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
483 { 15, 1, "BYPASS", "PLL Bypass", PRESENT_DEC, {
484 { MSR1(0), "Use PLL as Clocksource" },
485 { MSR1(1), "Use DOTREF as Clocksource" },
486 { BITVAL_EOT }
487 }},
488 { 14, 1, "PD", "Power Down", PRESENT_DEC, {
489 { MSR1(0), "PLL active" },
490 { MSR1(1), "PLL in power down mode" },
491 { BITVAL_EOT }
492 }},
493 { 13, 1, "RESETPLL", "PLL Reset", PRESENT_DEC, NOBITS },
494 { 12, 2, RESERVED },
495 { 10, 1, "DDRMODE", "DDR Mode", PRESENT_DEC, {
496 { MSR1(0), "DDR communication enabled" },
497 { MSR1(1), "Reserved" },
498 { BITVAL_EOT }
499 }},
500 { 9, 1, "VA_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
501 { MSR1(1), "CPU does not use GLIU1 FIFO" },
502 { MSR1(0), "The GLIU1 FIFO is used by the CPU" },
503 { BITVAL_EOT }
504 }},
505 { 8, 1, "PCI_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
506 { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
507 { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
508 { BITVAL_EOT }
509 }},
510 { 7, 1, "DSTALL", "Debug Stall", PRESENT_DEC, NOBITS },
511 { 6, 3, "BOOTSTRAP_STAT", "Bootstrap Status", PRESENT_BIN, NOBITS },
512 { 3, 1, "DOTPOSTDIV3", "DOTPLL Post-Divide by 3", PRESENT_DEC, NOBITS },
513 { 2, 1, "DOTPREMULT2", "DOTPLL Pre-Multiply by 2", PRESENT_DEC, NOBITS },
514 { 1, 1, "DOTPREDIV2", "DOTPLL Pre-Divide by 2", PRESENT_DEC, NOBITS },
515 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
516 { BITS_EOT }
517 }},
518 { MSR_EOT }
519};