Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame^] | 18 | #include <bootblock_common.h> |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 19 | #include <string.h> |
| 20 | #include <cbfs.h> |
| 21 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 23 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 24 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 25 | #include <southbridge/intel/bd82x6x/pch.h> |
| 26 | #include <ec/hp/kbc1126/ec.h> |
| 27 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 28 | void mainboard_late_rcba_config(void) |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 29 | { |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 30 | RCBA32(BUC) = 0x00000000; |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 31 | } |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 32 | |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 33 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 34 | { 1, 1, 0 }, |
| 35 | { 1, 0, 0 }, |
| 36 | { 1, 1, 1 }, |
| 37 | { 0, 1, 1 }, |
| 38 | { 0, 0, 2 }, |
| 39 | { 1, 0, 2 }, |
| 40 | { 0, 0, 3 }, |
| 41 | { 0, 0, 3 }, |
| 42 | { 1, 0, 4 }, /* B1P1: Digitizer */ |
| 43 | { 1, 0, 4 }, /* B1P2: wlan USB, EHCI debug */ |
| 44 | { 1, 1, 5 }, /* B1P3: Camera */ |
| 45 | { 0, 0, 5 }, /* B1P4 */ |
| 46 | { 1, 0, 6 }, /* B1P5: wwan USB */ |
| 47 | { 0, 0, 6 }, /* B1P6 */ |
| 48 | }; |
| 49 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame^] | 50 | void bootblock_mainboard_early_init(void) |
Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame] | 51 | { |
| 52 | kbc1126_enter_conf(); |
| 53 | kbc1126_mailbox_init(); |
| 54 | kbc1126_kbc_init(); |
| 55 | kbc1126_ec_init(); |
| 56 | kbc1126_pm1_init(); |
| 57 | kbc1126_exit_conf(); |
| 58 | } |
| 59 | |
| 60 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 61 | { |
| 62 | /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ |
| 63 | size_t spd_file_len = 0; |
| 64 | void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 65 | &spd_file_len); |
| 66 | |
| 67 | if (!spd_file || spd_file_len < sizeof(spd_raw_data)) |
| 68 | die("SPD data for C1S0 not found."); |
| 69 | |
| 70 | read_spd(&spd[0], 0x50, id_only); |
| 71 | memcpy(&spd[2], spd_file, spd_file_len); |
| 72 | } |