| Bill XIE | ee8da1c | 2017-12-16 10:15:18 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <string.h> |
| 19 | #include <cbfs.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 23 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 24 | #include <southbridge/intel/bd82x6x/pch.h> |
| 25 | #include <ec/hp/kbc1126/ec.h> |
| 26 | |
| 27 | void pch_enable_lpc(void) |
| 28 | { |
| 29 | /* |
| 30 | * CNF2 and CNF1 for Super I/O |
| 31 | * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC |
| 32 | */ |
| 33 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 34 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); |
| 35 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 36 | /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ |
| 37 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); |
| 38 | } |
| 39 | |
| 40 | void rcba_config(void) |
| 41 | { |
| 42 | /* Disable devices. */ |
| 43 | RCBA32(BUC) = 0x00000000; |
| 44 | RCBA32(FD) = 0x17f21feb; |
| 45 | |
| 46 | } |
| 47 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 48 | { 1, 1, 0 }, |
| 49 | { 1, 0, 0 }, |
| 50 | { 1, 1, 1 }, |
| 51 | { 0, 1, 1 }, |
| 52 | { 0, 0, 2 }, |
| 53 | { 1, 0, 2 }, |
| 54 | { 0, 0, 3 }, |
| 55 | { 0, 0, 3 }, |
| 56 | { 1, 0, 4 }, /* B1P1: Digitizer */ |
| 57 | { 1, 0, 4 }, /* B1P2: wlan USB, EHCI debug */ |
| 58 | { 1, 1, 5 }, /* B1P3: Camera */ |
| 59 | { 0, 0, 5 }, /* B1P4 */ |
| 60 | { 1, 0, 6 }, /* B1P5: wwan USB */ |
| 61 | { 0, 0, 6 }, /* B1P6 */ |
| 62 | }; |
| 63 | |
| 64 | void mainboard_early_init(int s3resume) |
| 65 | { |
| 66 | } |
| 67 | |
| 68 | void mainboard_config_superio(void) |
| 69 | { |
| 70 | kbc1126_enter_conf(); |
| 71 | kbc1126_mailbox_init(); |
| 72 | kbc1126_kbc_init(); |
| 73 | kbc1126_ec_init(); |
| 74 | kbc1126_pm1_init(); |
| 75 | kbc1126_exit_conf(); |
| 76 | } |
| 77 | |
| 78 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 79 | { |
| 80 | /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ |
| 81 | size_t spd_file_len = 0; |
| 82 | void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 83 | &spd_file_len); |
| 84 | |
| 85 | if (!spd_file || spd_file_len < sizeof(spd_raw_data)) |
| 86 | die("SPD data for C1S0 not found."); |
| 87 | |
| 88 | read_spd(&spd[0], 0x50, id_only); |
| 89 | memcpy(&spd[2], spd_file, spd_file_len); |
| 90 | } |