Angel Pons | 0fcb1b8 | 2020-04-03 01:21:20 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 2 | |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 3 | #include <device/device.h> |
Kyösti Mälkki | f7ca672 | 2017-09-10 06:30:54 +0300 | [diff] [blame] | 4 | |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 5 | #include <southbridge/amd/agesa/hudson/pci_devs.h> |
| 6 | #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> |
| 7 | #include <southbridge/amd/common/amd_pci_util.h> |
| 8 | #include <northbridge/amd/agesa/family16kb/pci_devs.h> |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 9 | |
| 10 | /*********************************************************** |
| 11 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 12 | * This table is responsible for physically routing the PIC and |
| 13 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 14 | * is read and written via registers 0xC00/0xC01 as an |
| 15 | * Index/Data pair. These values are chipset and mainboard |
| 16 | * dependent and should be updated accordingly. |
| 17 | * |
| 18 | * These values are used by the PCI configuration space, |
| 19 | * MP Tables. TODO: Make ACPI use these values too. |
| 20 | */ |
Kyösti Mälkki | e1e3289 | 2019-12-22 09:49:56 +0200 | [diff] [blame] | 21 | static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 22 | /* INTA# - INTH# */ |
| 23 | [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, |
| 24 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 25 | [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 26 | /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ |
| 27 | [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 28 | /* IMC INT0 - 5 */ |
| 29 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 30 | /* USB Devs 18/19/22 INTA-C */ |
| 31 | [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, |
| 32 | /* SATA */ |
| 33 | [0x41] = 0x0F, |
| 34 | }; |
| 35 | |
Kyösti Mälkki | e1e3289 | 2019-12-22 09:49:56 +0200 | [diff] [blame] | 36 | static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 37 | /* INTA# - INTH# */ |
| 38 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, |
| 39 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 40 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 41 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ |
| 42 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, |
| 43 | /* IMC INT0 - 5 */ |
| 44 | [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 45 | /* USB Devs 18/19/20/22 INTA-C */ |
| 46 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, |
| 47 | /* SATA */ |
| 48 | [0x41] = 0x13 |
| 49 | }; |
| 50 | |
| 51 | /* |
| 52 | * This table defines the index into the picr/intr_data |
| 53 | * tables for each device. Any enabled device and slot |
| 54 | * that uses hardware interrupts should have an entry |
| 55 | * in this table to define its index into the FCH |
| 56 | * PCI_INTR register 0xC00/0xC01. This index will define |
| 57 | * the interrupt that it should use. Putting PIRQ_A into |
| 58 | * the PIN A index for a device will tell that device to |
| 59 | * use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 60 | */ |
| 61 | static const struct pirq_struct mainboard_pirq_data[] = { |
| 62 | /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ |
| 63 | {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ |
| 64 | {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ |
| 65 | {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ |
| 66 | {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ |
| 67 | {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ |
| 68 | {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ |
| 69 | {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ |
| 70 | {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ |
| 71 | {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ |
| 72 | {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ |
| 73 | {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ |
| 74 | {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ |
| 75 | {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ |
| 76 | {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ |
| 77 | {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ |
| 78 | {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ |
| 79 | }; |
| 80 | |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 81 | /* PIRQ Setup */ |
| 82 | static void pirq_setup(void) |
| 83 | { |
| 84 | pirq_data_ptr = mainboard_pirq_data; |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 85 | pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 86 | intr_data_ptr = mainboard_intr_data; |
| 87 | picr_data_ptr = mainboard_picr_data; |
| 88 | } |
| 89 | |
| 90 | /********************************************** |
| 91 | * enable the dedicated function in mainboard. |
| 92 | **********************************************/ |
Elyes HAOUAS | 5a0757c | 2018-05-04 20:05:33 +0200 | [diff] [blame] | 93 | static void mainboard_enable(struct device *dev) |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 94 | { |
Kyösti Mälkki | 595ef3d | 2015-05-27 12:44:16 +0300 | [diff] [blame] | 95 | /* Initialize the PIRQ data structures for consumption */ |
| 96 | pirq_setup(); |
| 97 | } |
| 98 | |
| 99 | struct chip_operations mainboard_ops = { |
| 100 | .enable_dev = mainboard_enable, |
| 101 | }; |