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review.coreboot.org / coreboot / f9decbb0c720662d8e71fe221aef55b7ecf76196 / . / src / mainboard / amd / olivehill / dsdt.asl
blob: c86cf27f67c2c10163037434acfa22b7b275a8e5 [file] [log] [blame]
Angel Pons5c596802020-04-03 01:21:01 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]2
3/* DefinitionBlock Statement */
Furquan Shaikh76cedd22020-05-02 10:24:23 -0700[diff] [blame]4#include <acpi/acpi.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]5DefinitionBlock (
Elyes HAOUAS2bfaabc2020-10-01 17:03:55 +0200[diff] [blame]6 "dsdt.aml",
Elyes HAOUAS37509d72020-10-01 17:11:56 +0200[diff] [blame]7 "DSDT",
Elyes HAOUAS90d00de2020-10-05 16:38:53 +0200[diff] [blame]8 ACPI_DSDT_REV_2,
Elyes HAOUAS6d19a202018-11-22 11:15:29 +0100[diff] [blame]9 OEM_ID,
10 ACPI_TABLE_CREATOR,
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]11 0x00010001 /* OEM Revision */
12 )
13{ /* Start of ASL file */
Kyösti Mälkkicf246d52021-01-21 08:17:00 +0200[diff] [blame]14 #include <acpi/dsdt_top.asl>
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300[diff] [blame]15
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]16 /* Globals for the platform */
17 #include "acpi/mainboard.asl"
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]18
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]19 /* Describe the USB Overcurrent pins */
20 #include "acpi/usb_oc.asl"
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]21
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]22 /* PCI IRQ mapping for the Southbridge */
23 #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]24
Michał Żygowski9550e972020-03-20 13:56:46 +0100[diff] [blame]25 /* Describe the processor tree (\_SB) */
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]26 #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]27
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]28 /* Contains the supported sleep states for this chipset */
Kyösti Mälkki390ba042017-08-07 21:42:46 +0300[diff] [blame]29 #include <southbridge/amd/common/acpi/sleepstates.asl>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]30
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]31 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
32 #include "acpi/sleep.asl"
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]33
34 /* System Bus */
35 Scope(\_SB) { /* Start \_SB scope */
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame]36 /* global utility methods expected within the \_SB scope */
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]37 #include <arch/x86/acpi/globutil.asl>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]38
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]39 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
40 #include "acpi/routing.asl"
41
Alexandru Gagniuc44f2fab2014-04-18 01:42:19 -0500[diff] [blame]42 Device(PWRB) {
43 Name(_HID, EISAID("PNP0C0C"))
44 Name(_UID, 0xAA)
45 Name(_PRW, Package () {3, 0x04})
46 Name(_STA, 0x0B)
47 }
48
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]49 Device(PCI0) {
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]50 /* Describe the AMD Northbridge */
51 #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]52
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]53 /* Describe the AMD Fusion Controller Hub Southbridge */
54 #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]55 }
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]56
57 /* Describe PCI INT[A-H] for the Southbridge */
58 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
59
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]60 } /* End \_SB scope */
61
Mike Loptienac90d802013-07-17 15:14:59 -0600[diff] [blame]62 /* Describe SMBUS for the Southbridge */
63 #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
64
65 /* Define the General Purpose Events for the platform */
66 #include "acpi/gpe.asl"
67
68 /* Define the Thermal zones and methods for the platform */
69 #include "acpi/thermal.asl"
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]70}
71/* End of ASL file */