Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 5 | #include <southbridge/intel/bd82x6x/pch.h> |
| 6 | |
| 7 | void early_init_dmi(void) |
| 8 | { |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 9 | int i; |
| 10 | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 11 | for (i = 0; i < 2; i++) { |
| 12 | DMIBAR32(0x0914 + (i << 5)) |= (1 << 31); |
| 13 | } |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 14 | |
| 15 | for (i = 0; i < 4; i++) { |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 16 | DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000; |
| 17 | DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 18 | } |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 19 | DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 20 | |
| 21 | for (i = 0; i < 2; i++) { |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 22 | DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000; |
| 23 | DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000; |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 24 | } |
| 25 | |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 26 | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 27 | for (i = 0; i < 2; i++) { |
| 28 | DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000; |
| 29 | } |
| 30 | |
| 31 | for (i = 0; i < 2; i++) { |
| 32 | DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec |
| 33 | DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec; |
| 34 | DMIBAR32(0x090c + (i << 5)); // !!! = 0x00000208 |
| 35 | DMIBAR32(0x090c + (i << 5)) = 0x00000128; |
| 36 | } |
| 37 | |
| 38 | for (i = 0; i < 2; i++) { |
| 39 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 |
| 40 | DMIBAR32(0x0700 + (i << 5)) = 0x46139008; |
| 41 | } |
| 42 | |
Elyes HAOUAS | fa1f721 | 2019-05-22 15:40:54 +0200 | [diff] [blame] | 43 | DMIBAR32(0x0c04); // !!! = 0x2e680008 |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 44 | DMIBAR32(0x0c04) = 0x2e680008; |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 45 | |
| 46 | for (i = 0; i < 2; i++) { |
| 47 | DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec |
| 48 | DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec; |
| 49 | } |
| 50 | |
| 51 | for (i = 0; i < 2; i++) { |
| 52 | DMIBAR32(0x0910 + (i << 5)); // !!! = 0x00006300 |
| 53 | DMIBAR32(0x0910 + (i << 5)) = 0x00004300; |
| 54 | } |
| 55 | |
| 56 | for (i = 0; i < 4; i++) { |
| 57 | DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042010 |
| 58 | DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; |
| 59 | } |
| 60 | |
Elyes HAOUAS | fa1f721 | 2019-05-22 15:40:54 +0200 | [diff] [blame] | 61 | DMIBAR32(0x0c00); // !!! = 0x29700c08 |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 62 | DMIBAR32(0x0c00) = 0x29700c08; |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 63 | |
| 64 | for (i = 0; i < 4; i++) { |
| 65 | DMIBAR32(0x0a04 + (i << 4)); // !!! = 0x0c0708f0 |
| 66 | DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0; |
| 67 | } |
| 68 | |
| 69 | for (i = 0; i < 2; i++) { |
| 70 | DMIBAR32(0x0900 + (i << 5)); // !!! = 0x50000000 |
| 71 | DMIBAR32(0x0900 + (i << 5)) = 0x50000000; |
| 72 | } |
| 73 | |
| 74 | for (i = 0; i < 2; i++) { |
| 75 | DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff |
| 76 | DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; |
| 77 | } |
| 78 | |
| 79 | for (i = 0; i < 4; i++) { |
| 80 | DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 |
| 81 | DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; |
| 82 | } |
| 83 | |
| 84 | for (i = 0; i < 2; i++) { |
| 85 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 |
| 86 | DMIBAR32(0x0700 + (i << 5)) = 0x46139008; |
| 87 | } |
| 88 | |
| 89 | for (i = 0; i < 2; i++) { |
| 90 | DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1842ec |
| 91 | DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec; |
| 92 | } |
| 93 | |
| 94 | for (i = 0; i < 4; i++) { |
| 95 | DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 |
| 96 | DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; |
| 97 | } |
| 98 | |
| 99 | for (i = 0; i < 2; i++) { |
| 100 | DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff |
| 101 | DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; |
| 102 | } |
| 103 | |
Elyes HAOUAS | fa1f721 | 2019-05-22 15:40:54 +0200 | [diff] [blame] | 104 | DMIBAR32(0x0c00); // !!! = 0x29700c08 |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 105 | DMIBAR32(0x0c00) = 0x29700c08; |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 106 | |
Elyes HAOUAS | fa1f721 | 2019-05-22 15:40:54 +0200 | [diff] [blame] | 107 | DMIBAR32(0x0c0c); // !!! = 0x16063400 |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 108 | DMIBAR32(0x0c0c) = 0x00063400; |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 109 | |
| 110 | for (i = 0; i < 2; i++) { |
| 111 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 |
| 112 | DMIBAR32(0x0700 + (i << 5)) = 0x46339008; |
| 113 | } |
| 114 | |
| 115 | for (i = 0; i < 2; i++) { |
| 116 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46339008 |
| 117 | DMIBAR32(0x0700 + (i << 5)) = 0x45339008; |
| 118 | } |
| 119 | |
| 120 | for (i = 0; i < 2; i++) { |
| 121 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45339008 |
| 122 | DMIBAR32(0x0700 + (i << 5)) = 0x453b9008; |
| 123 | } |
| 124 | |
| 125 | for (i = 0; i < 2; i++) { |
| 126 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x453b9008 |
| 127 | DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008; |
| 128 | } |
| 129 | |
| 130 | for (i = 0; i < 2; i++) { |
| 131 | DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45bb9008 |
| 132 | DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008; |
| 133 | } |
| 134 | |
| 135 | for (i = 0; i < 2; i++) { |
| 136 | DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 |
| 137 | DMIBAR32(0x0914 + (i << 5)) = 0x9021a280; |
| 138 | } |
| 139 | |
| 140 | for (i = 0; i < 2; i++) { |
| 141 | DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 |
| 142 | DMIBAR32(0x0914 + (i << 5)) = 0x9821a280; |
| 143 | } |
| 144 | |
| 145 | for (i = 0; i < 4; i++) { |
| 146 | DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 |
| 147 | DMIBAR32(0x0a00 + (i << 4)) = 0x03242018; |
| 148 | } |
| 149 | |
Elyes HAOUAS | fa1f721 | 2019-05-22 15:40:54 +0200 | [diff] [blame] | 150 | DMIBAR32(0x0258); // !!! = 0x40000600 |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 151 | DMIBAR32(0x0258) = 0x60000600; |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 152 | |
| 153 | for (i = 0; i < 2; i++) { |
| 154 | DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1846ec |
| 155 | DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec; |
| 156 | DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9821a280 |
| 157 | DMIBAR32(0x0914 + (i << 5)) = 0x98200280; |
| 158 | } |
| 159 | |
Angel Pons | f950a7e | 2020-09-14 17:15:37 +0200 | [diff] [blame^] | 160 | DMIBAR32(DMIL0SLAT); // !!! = 0x00c26460 |
| 161 | DMIBAR32(DMIL0SLAT) = 0x00c2403c; |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 162 | |
| 163 | early_pch_init_native_dmi_pre(); |
| 164 | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 165 | /* Write once settings */ |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 166 | DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 167 | (2 << 0) | // 5GT/s |
| 168 | (2 << 12) | // L0s 128 ns to less than 256 ns |
| 169 | (2 << 15); // L1 2 us to less than 4 us |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 170 | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 171 | DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 172 | while (DMIBAR16(DMILSTS) & TXTRN) |
| 173 | ; |
| 174 | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 175 | DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 176 | while (DMIBAR16(DMILSTS) & TXTRN) |
| 177 | ; |
| 178 | |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 179 | const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; |
| 180 | const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500; |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 181 | |
| 182 | printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); |
| 183 | /* |
| 184 | * Virtual Channel resources must match settings in RCBA! |
| 185 | * |
Angel Pons | e82b02c | 2020-03-18 13:09:39 +0100 | [diff] [blame] | 186 | * Channel Vp and Vm are documented in: |
| 187 | * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium |
| 188 | * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 189 | */ |
| 190 | |
| 191 | /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ |
| 192 | DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; |
| 193 | /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ |
| 194 | DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); |
| 195 | /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ |
| 196 | DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); |
| 197 | /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ |
| 198 | DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); |
| 199 | |
| 200 | /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ |
| 201 | DMIBAR8(DMIPVCCAP1) |= 1; |
| 202 | |
| 203 | early_pch_init_native_dmi_post(); |
| 204 | |
| 205 | /* |
| 206 | * BIOS Requirement: Check if DMI VC Negotiation was successful. |
| 207 | * Wait for virtual channels negotiation pending. |
| 208 | */ |
| 209 | while (DMIBAR16(DMIVC0RSTS) & VC0NP) |
| 210 | ; |
| 211 | while (DMIBAR16(DMIVC1RSTS) & VC1NP) |
| 212 | ; |
| 213 | while (DMIBAR16(DMIVCPRSTS) & VCPNP) |
| 214 | ; |
| 215 | while (DMIBAR16(DMIVCMRSTS) & VCMNP) |
| 216 | ; |
| 217 | } |