Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 18 | #include <southbridge/intel/bd82x6x/pch.h> |
| 19 | |
| 20 | void early_init_dmi(void) |
| 21 | { |
| 22 | volatile u32 tmp; |
| 23 | int i; |
| 24 | |
| 25 | DMIBAR32(0x0914) |= 0x80000000; |
| 26 | DMIBAR32(0x0934) |= 0x80000000; |
| 27 | |
| 28 | for (i = 0; i < 4; i++) { |
| 29 | DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; |
| 30 | DMIBAR32(0x0a04 + (i << 4)) |= 0x800; |
| 31 | } |
| 32 | DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; |
| 33 | |
| 34 | for (i = 0; i < 2; i++) { |
| 35 | DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; |
| 36 | DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; |
| 37 | } |
| 38 | |
| 39 | DMIBAR32(0x090c) &= 0xfe1fffff; |
| 40 | DMIBAR32(0x092c) &= 0xfe1fffff; |
| 41 | |
| 42 | tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec |
| 43 | DMIBAR32(0x0904) = 0x7a1842ec; |
| 44 | tmp = DMIBAR32(0x090c); // !!! = 0x00000208 |
| 45 | DMIBAR32(0x090c) = 0x00000128; |
| 46 | tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec |
| 47 | DMIBAR32(0x0924) = 0x7a1842ec; |
| 48 | tmp = DMIBAR32(0x092c); // !!! = 0x00000208 |
| 49 | DMIBAR32(0x092c) = 0x00000128; |
| 50 | tmp = DMIBAR32(0x0700); // !!! = 0x46139008 |
| 51 | DMIBAR32(0x0700) = 0x46139008; |
| 52 | tmp = DMIBAR32(0x0720); // !!! = 0x46139008 |
| 53 | DMIBAR32(0x0720) = 0x46139008; |
| 54 | tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 |
| 55 | DMIBAR32(0x0c04) = 0x2e680008; |
| 56 | tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec |
| 57 | DMIBAR32(0x0904) = 0x3a1842ec; |
| 58 | tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec |
| 59 | DMIBAR32(0x0924) = 0x3a1842ec; |
| 60 | tmp = DMIBAR32(0x0910); // !!! = 0x00006300 |
| 61 | DMIBAR32(0x0910) = 0x00004300; |
| 62 | tmp = DMIBAR32(0x0930); // !!! = 0x00006300 |
| 63 | DMIBAR32(0x0930) = 0x00004300; |
| 64 | tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 |
| 65 | DMIBAR32(0x0a00) = 0x03042018; |
| 66 | tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 |
| 67 | DMIBAR32(0x0a10) = 0x03042018; |
| 68 | tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 |
| 69 | DMIBAR32(0x0a20) = 0x03042018; |
| 70 | tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 |
| 71 | DMIBAR32(0x0a30) = 0x03042018; |
| 72 | tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 |
| 73 | DMIBAR32(0x0c00) = 0x29700c08; |
| 74 | tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 |
| 75 | DMIBAR32(0x0a04) = 0x0c0718f0; |
| 76 | tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 |
| 77 | DMIBAR32(0x0a14) = 0x0c0718f0; |
| 78 | tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 |
| 79 | DMIBAR32(0x0a24) = 0x0c0718f0; |
| 80 | tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 |
| 81 | DMIBAR32(0x0a34) = 0x0c0718f0; |
| 82 | tmp = DMIBAR32(0x0900); // !!! = 0x50000000 |
| 83 | DMIBAR32(0x0900) = 0x50000000; |
| 84 | tmp = DMIBAR32(0x0920); // !!! = 0x50000000 |
| 85 | DMIBAR32(0x0920) = 0x50000000; |
| 86 | tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff |
| 87 | DMIBAR32(0x0908) = 0x51ffffff; |
| 88 | tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff |
| 89 | DMIBAR32(0x0928) = 0x51ffffff; |
| 90 | tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 |
| 91 | DMIBAR32(0x0a00) = 0x03042018; |
| 92 | tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 |
| 93 | DMIBAR32(0x0a10) = 0x03042018; |
| 94 | tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 |
| 95 | DMIBAR32(0x0a20) = 0x03042018; |
| 96 | tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 |
| 97 | DMIBAR32(0x0a30) = 0x03042018; |
| 98 | tmp = DMIBAR32(0x0700); // !!! = 0x46139008 |
| 99 | DMIBAR32(0x0700) = 0x46139008; |
| 100 | tmp = DMIBAR32(0x0720); // !!! = 0x46139008 |
| 101 | DMIBAR32(0x0720) = 0x46139008; |
| 102 | tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec |
| 103 | DMIBAR32(0x0904) = 0x3a1846ec; |
| 104 | tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec |
| 105 | DMIBAR32(0x0924) = 0x3a1846ec; |
| 106 | tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 |
| 107 | DMIBAR32(0x0a00) = 0x03042018; |
| 108 | tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 |
| 109 | DMIBAR32(0x0a10) = 0x03042018; |
| 110 | tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 |
| 111 | DMIBAR32(0x0a20) = 0x03042018; |
| 112 | tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 |
| 113 | DMIBAR32(0x0a30) = 0x03042018; |
| 114 | tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff |
| 115 | DMIBAR32(0x0908) = 0x51ffffff; |
| 116 | tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff |
| 117 | DMIBAR32(0x0928) = 0x51ffffff; |
| 118 | tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 |
| 119 | DMIBAR32(0x0c00) = 0x29700c08; |
| 120 | tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 |
| 121 | DMIBAR32(0x0c0c) = 0x00063400; |
| 122 | tmp = DMIBAR32(0x0700); // !!! = 0x46139008 |
| 123 | DMIBAR32(0x0700) = 0x46339008; |
| 124 | tmp = DMIBAR32(0x0720); // !!! = 0x46139008 |
| 125 | DMIBAR32(0x0720) = 0x46339008; |
| 126 | tmp = DMIBAR32(0x0700); // !!! = 0x46339008 |
| 127 | DMIBAR32(0x0700) = 0x45339008; |
| 128 | tmp = DMIBAR32(0x0720); // !!! = 0x46339008 |
| 129 | DMIBAR32(0x0720) = 0x45339008; |
| 130 | tmp = DMIBAR32(0x0700); // !!! = 0x45339008 |
| 131 | DMIBAR32(0x0700) = 0x453b9008; |
| 132 | tmp = DMIBAR32(0x0720); // !!! = 0x45339008 |
| 133 | DMIBAR32(0x0720) = 0x453b9008; |
| 134 | tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 |
| 135 | DMIBAR32(0x0700) = 0x45bb9008; |
| 136 | tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 |
| 137 | DMIBAR32(0x0720) = 0x45bb9008; |
| 138 | tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 |
| 139 | DMIBAR32(0x0700) = 0x45fb9008; |
| 140 | tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 |
| 141 | DMIBAR32(0x0720) = 0x45fb9008; |
| 142 | tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 |
| 143 | DMIBAR32(0x0914) = 0x9021a280; |
| 144 | tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 |
| 145 | DMIBAR32(0x0934) = 0x9021a280; |
| 146 | tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 |
| 147 | DMIBAR32(0x0914) = 0x9821a280; |
| 148 | tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 |
| 149 | DMIBAR32(0x0934) = 0x9821a280; |
| 150 | tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 |
| 151 | DMIBAR32(0x0a00) = 0x03242018; |
| 152 | tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 |
| 153 | DMIBAR32(0x0a10) = 0x03242018; |
| 154 | tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 |
| 155 | DMIBAR32(0x0a20) = 0x03242018; |
| 156 | tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 |
| 157 | DMIBAR32(0x0a30) = 0x03242018; |
| 158 | tmp = DMIBAR32(0x0258); // !!! = 0x40000600 |
| 159 | DMIBAR32(0x0258) = 0x60000600; |
| 160 | tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec |
| 161 | DMIBAR32(0x0904) = 0x2a1846ec; |
| 162 | tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 |
| 163 | DMIBAR32(0x0914) = 0x98200280; |
| 164 | tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec |
| 165 | DMIBAR32(0x0924) = 0x2a1846ec; |
| 166 | tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 |
| 167 | DMIBAR32(0x0934) = 0x98200280; |
| 168 | tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 |
| 169 | DMIBAR32(0x022c) = 0x00c2403c; |
| 170 | |
| 171 | early_pch_init_native_dmi_pre(); |
| 172 | |
| 173 | /* Write once settings. */ |
| 174 | DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | |
| 175 | (2 << 0) | // 5GT/s |
| 176 | (2 << 12) | // L0s 128 ns to less than 256 ns |
| 177 | (2 << 15); // L1 2 us to less than 4 us |
| 178 | |
| 179 | DMIBAR8(DMILCTL) |= 0x20; // Retrain link |
| 180 | while (DMIBAR16(DMILSTS) & TXTRN) |
| 181 | ; |
| 182 | |
| 183 | DMIBAR8(DMILCTL) |= 0x20; // Retrain link |
| 184 | while (DMIBAR16(DMILSTS) & TXTRN) |
| 185 | ; |
| 186 | |
| 187 | const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; |
| 188 | const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; |
| 189 | |
| 190 | printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); |
| 191 | /* |
| 192 | * Virtual Channel resources must match settings in RCBA! |
| 193 | * |
| 194 | * Channel Vp and Vm are documented in |
| 195 | * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel |
| 196 | * Pentium Processor Family, and Desktop Intel Celeron Processor Family |
| 197 | * Vol. 2" |
| 198 | */ |
| 199 | |
| 200 | /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ |
| 201 | DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; |
| 202 | /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ |
| 203 | DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); |
| 204 | /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ |
| 205 | DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); |
| 206 | /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ |
| 207 | DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); |
| 208 | |
| 209 | /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ |
| 210 | DMIBAR8(DMIPVCCAP1) |= 1; |
| 211 | |
| 212 | early_pch_init_native_dmi_post(); |
| 213 | |
| 214 | /* |
| 215 | * BIOS Requirement: Check if DMI VC Negotiation was successful. |
| 216 | * Wait for virtual channels negotiation pending. |
| 217 | */ |
| 218 | while (DMIBAR16(DMIVC0RSTS) & VC0NP) |
| 219 | ; |
| 220 | while (DMIBAR16(DMIVC1RSTS) & VC1NP) |
| 221 | ; |
| 222 | while (DMIBAR16(DMIVCPRSTS) & VCPNP) |
| 223 | ; |
| 224 | while (DMIBAR16(DMIVCMRSTS) & VCMNP) |
| 225 | ; |
| 226 | } |