Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 5 | #include <commonlib/helpers.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <delay.h> |
| 9 | #include <cpu/intel/model_206ax/model_206ax.h> |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 10 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
| 13 | #include <device/pci_ids.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | #include "sandybridge.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 16 | #include <cpu/intel/smm_reloc.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 17 | |
| 18 | static int bridge_revision_id = -1; |
| 19 | |
Kyösti Mälkki | f7bfc34 | 2013-10-18 11:02:46 +0300 | [diff] [blame] | 20 | /* IGD UMA memory */ |
| 21 | static uint64_t uma_memory_base = 0; |
| 22 | static uint64_t uma_memory_size = 0; |
| 23 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 24 | int bridge_silicon_revision(void) |
| 25 | { |
| 26 | if (bridge_revision_id < 0) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 27 | uint8_t stepping = cpuid_eax(1) & 0x0f; |
| 28 | uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); |
| 29 | bridge_revision_id = (bridge_id & 0xf0) | stepping; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 30 | } |
| 31 | return bridge_revision_id; |
| 32 | } |
| 33 | |
| 34 | /* Reserve everything between A segment and 1MB: |
| 35 | * |
| 36 | * 0xa0000 - 0xbffff: legacy VGA |
| 37 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 38 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 39 | */ |
| 40 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 41 | static const int legacy_hole_size_k = 384; |
| 42 | |
Angel Pons | 8bf1976 | 2020-08-03 14:55:18 +0200 | [diff] [blame] | 43 | int decode_pcie_bar(u32 *const base, u32 *const len) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 44 | { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | *base = 0; |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 46 | *len = 0; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 47 | |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 48 | struct device *dev = pcidev_on_root(0, 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 49 | if (!dev) |
| 50 | return 0; |
| 51 | |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 52 | const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 53 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 54 | /* MMCFG not supported or not enabled */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 55 | if (!(pciexbar_reg & (1 << 0))) |
| 56 | return 0; |
| 57 | |
| 58 | switch ((pciexbar_reg >> 1) & 3) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 59 | case 0: /* 256MB */ |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 60 | *base = pciexbar_reg & (0x0f << 28); |
| 61 | *len = 256 * MiB; |
| 62 | return 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 63 | case 1: /* 128M */ |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 64 | *base = pciexbar_reg & (0x1f << 27); |
| 65 | *len = 128 * MiB; |
| 66 | return 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 67 | case 2: /* 64M */ |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 68 | *base = pciexbar_reg & (0x3f << 26); |
| 69 | *len = 64 * MiB; |
| 70 | return 1; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | return 0; |
| 74 | } |
| 75 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 76 | static const char *northbridge_acpi_name(const struct device *dev) |
| 77 | { |
| 78 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 79 | return "PCI0"; |
| 80 | |
| 81 | if (dev->path.type != DEVICE_PATH_PCI) |
| 82 | return NULL; |
| 83 | |
| 84 | switch (dev->path.pci.devfn) { |
| 85 | case PCI_DEVFN(0, 0): |
| 86 | return "MCHC"; |
| 87 | } |
| 88 | |
| 89 | return NULL; |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * TODO We could determine how many PCIe busses we need in the bar. |
| 94 | * For now, that number is hardcoded to a max of 64. |
| 95 | */ |
| 96 | static struct device_operations pci_domain_ops = { |
| 97 | .read_resources = pci_domain_read_resources, |
| 98 | .set_resources = pci_domain_set_resources, |
| 99 | .scan_bus = pci_domain_scan_bus, |
| 100 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 101 | .acpi_name = northbridge_acpi_name, |
| 102 | }; |
| 103 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 104 | static void add_fixed_resources(struct device *dev, int index) |
| 105 | { |
Kyösti Mälkki | 7f189cc | 2012-07-27 13:12:03 +0300 | [diff] [blame] | 106 | mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 107 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 108 | mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); |
| 109 | |
| 110 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 111 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 112 | #if CONFIG(CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 113 | reserved_ram_resource(dev, index++, |
| 114 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 115 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 116 | #endif |
| 117 | |
Nico Huber | 593e7de | 2015-11-04 15:46:00 +0100 | [diff] [blame] | 118 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 119 | /* Required for SandyBridge sighting 3715511 */ |
| 120 | bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); |
| 121 | bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); |
| 122 | } |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 123 | |
| 124 | /* Reserve IOMMU BARs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 125 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 126 | if (!(capid0_a & (1 << 23))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 127 | mmio_resource(dev, index++, GFXVT_BASE >> 10, 4); |
| 128 | mmio_resource(dev, index++, VTVC0_BASE >> 10, 4); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 129 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 130 | } |
| 131 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 132 | static void mc_read_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 133 | { |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 134 | u32 pcie_config_base, pcie_config_len; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 135 | uint64_t tom, me_base, touud; |
| 136 | uint32_t tseg_base, uma_size, tolud; |
| 137 | uint16_t ggc; |
| 138 | unsigned long long tomk; |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 139 | unsigned long index = 3; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 140 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 141 | pci_dev_read_resources(dev); |
| 142 | |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 143 | if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { |
| 144 | const int buses = pcie_config_len / MiB; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 145 | struct resource *resource = new_resource(dev, PCIEXBAR); |
| 146 | mmconf_resource_init(resource, pcie_config_base, buses); |
| 147 | } |
| 148 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 149 | /* Total Memory 2GB example: |
| 150 | * |
| 151 | * 00000000 0000MB-1992MB 1992MB RAM (writeback) |
| 152 | * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) |
| 153 | * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) |
| 154 | * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) |
| 155 | * 7f200000 2034MB TOLUD |
| 156 | * 7f800000 2040MB MEBASE |
| 157 | * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) |
| 158 | * 80000000 2048MB TOM |
| 159 | * 100000000 4096MB-4102MB 6MB RAM (writeback) |
| 160 | * |
| 161 | * Total Memory 4GB example: |
| 162 | * |
| 163 | * 00000000 0000MB-2768MB 2768MB RAM (writeback) |
| 164 | * ad000000 2768MB-2776MB 8MB TSEG (SMRR) |
| 165 | * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) |
| 166 | * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) |
| 167 | * afa00000 2810MB TOLUD |
| 168 | * ff800000 4088MB MEBASE |
| 169 | * ff800000 4088MB-4096MB 8MB ME UMA (uncached) |
| 170 | * 100000000 4096MB TOM |
| 171 | * 100000000 4096MB-5374MB 1278MB RAM (writeback) |
| 172 | * 14fe00000 5368MB TOUUD |
| 173 | */ |
| 174 | |
| 175 | /* Top of Upper Usable DRAM, including remap */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 176 | touud = pci_read_config32(dev, TOUUD + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 177 | touud <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 178 | touud |= pci_read_config32(dev, TOUUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 179 | |
| 180 | /* Top of Lower Usable DRAM */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 181 | tolud = pci_read_config32(dev, TOLUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 182 | |
| 183 | /* Top of Memory - does not account for any UMA */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 184 | tom = pci_read_config32(dev, TOM + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 185 | tom <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 186 | tom |= pci_read_config32(dev, TOM); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 187 | |
| 188 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 189 | touud, tolud, tom); |
| 190 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 191 | /* ME UMA needs excluding if total memory < 4GB */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 192 | me_base = pci_read_config32(dev, MESEG_BASE + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 193 | me_base <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 194 | me_base |= pci_read_config32(dev, MESEG_BASE); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 195 | |
| 196 | printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); |
| 197 | |
Patrick Rudolph | 240766a | 2015-10-15 15:33:25 +0200 | [diff] [blame] | 198 | uma_memory_base = tolud; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 199 | tomk = tolud >> 10; |
| 200 | if (me_base == tolud) { |
| 201 | /* ME is from MEBASE-TOM */ |
| 202 | uma_size = (tom - me_base) >> 10; |
| 203 | /* Increment TOLUD to account for ME as RAM */ |
| 204 | tolud += uma_size << 10; |
| 205 | /* UMA starts at old TOLUD */ |
| 206 | uma_memory_base = tomk * 1024ULL; |
| 207 | uma_memory_size = uma_size * 1024ULL; |
| 208 | printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", |
| 209 | me_base, uma_size >> 10); |
| 210 | } |
| 211 | |
| 212 | /* Graphics memory comes next */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 213 | ggc = pci_read_config16(dev, GGC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 214 | if (!(ggc & 2)) { |
| 215 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 216 | |
| 217 | /* Graphics memory */ |
| 218 | uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; |
| 219 | printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); |
| 220 | tomk -= uma_size; |
| 221 | uma_memory_base = tomk * 1024ULL; |
| 222 | uma_memory_size += uma_size * 1024ULL; |
| 223 | |
| 224 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 225 | uma_size = ((ggc >> 8) & 0x3) * 1024ULL; |
| 226 | tomk -= uma_size; |
| 227 | uma_memory_base = tomk * 1024ULL; |
| 228 | uma_memory_size += uma_size * 1024ULL; |
| 229 | printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); |
| 230 | } |
| 231 | |
| 232 | /* Calculate TSEG size from its base which must be below GTT */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 233 | tseg_base = pci_read_config32(dev, TSEGMB); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 234 | uma_size = (uma_memory_base - tseg_base) >> 10; |
| 235 | tomk -= uma_size; |
| 236 | uma_memory_base = tomk * 1024ULL; |
| 237 | uma_memory_size += uma_size * 1024ULL; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 238 | printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 239 | |
| 240 | printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); |
| 241 | |
| 242 | /* Report the memory regions */ |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 243 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 244 | ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, |
| 245 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 246 | |
| 247 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 248 | * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. |
| 249 | * TOUUD will account for both memory chunks. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 250 | */ |
| 251 | touud >>= 10; /* Convert to KB */ |
| 252 | if (touud > 4096 * 1024) { |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 253 | ram_resource(dev, index++, 4096 * 1024, touud - (4096 * 1024)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 254 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 255 | } |
| 256 | |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 257 | add_fixed_resources(dev, index++); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 258 | } |
| 259 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 260 | static void northbridge_dmi_init(struct device *dev) |
| 261 | { |
| 262 | u32 reg32; |
| 263 | |
| 264 | /* Clear error status bits */ |
| 265 | DMIBAR32(0x1c4) = 0xffffffff; |
| 266 | DMIBAR32(0x1d0) = 0xffffffff; |
| 267 | |
| 268 | /* Steps prior to DMI ASPM */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 269 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 270 | reg32 = DMIBAR32(0x250); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 271 | reg32 &= ~((1 << 22) | (1 << 20)); |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 272 | reg32 |= (1 << 21); |
| 273 | DMIBAR32(0x250) = reg32; |
| 274 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 275 | |
| 276 | reg32 = DMIBAR32(0x238); |
| 277 | reg32 |= (1 << 29); |
| 278 | DMIBAR32(0x238) = reg32; |
| 279 | |
| 280 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 281 | reg32 = DMIBAR32(0x1f8); |
| 282 | reg32 |= (1 << 16); |
| 283 | DMIBAR32(0x1f8) = reg32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 284 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 285 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 286 | reg32 = DMIBAR32(0x1f8); |
| 287 | reg32 &= ~(1 << 26); |
| 288 | reg32 |= (1 << 16); |
| 289 | DMIBAR32(0x1f8) = reg32; |
| 290 | |
| 291 | reg32 = DMIBAR32(0x1fc); |
| 292 | reg32 |= (1 << 12) | (1 << 23); |
| 293 | DMIBAR32(0x1fc) = reg32; |
| 294 | } |
| 295 | |
| 296 | /* Enable ASPM on SNB link, should happen before PCH link */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 297 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 298 | reg32 = DMIBAR32(0xd04); |
| 299 | reg32 |= (1 << 4); |
| 300 | DMIBAR32(0xd04) = reg32; |
| 301 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 302 | |
| 303 | reg32 = DMIBAR32(0x88); |
| 304 | reg32 |= (1 << 1) | (1 << 0); |
| 305 | DMIBAR32(0x88) = reg32; |
| 306 | } |
| 307 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 308 | /* Disable unused PEG devices based on devicetree */ |
| 309 | static void disable_peg(void) |
| 310 | { |
| 311 | struct device *dev; |
| 312 | u32 reg; |
| 313 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 314 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 315 | reg = pci_read_config32(dev, DEVEN); |
| 316 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 317 | dev = pcidev_on_root(1, 2); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 318 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 319 | printk(BIOS_DEBUG, "Disabling PEG12.\n"); |
| 320 | reg &= ~DEVEN_PEG12; |
| 321 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 322 | dev = pcidev_on_root(1, 1); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 323 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 324 | printk(BIOS_DEBUG, "Disabling PEG11.\n"); |
| 325 | reg &= ~DEVEN_PEG11; |
| 326 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 327 | dev = pcidev_on_root(1, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 328 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 329 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 330 | reg &= ~DEVEN_PEG10; |
| 331 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 332 | dev = pcidev_on_root(2, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 333 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 334 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 335 | reg &= ~DEVEN_IGD; |
| 336 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 337 | dev = pcidev_on_root(4, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 338 | if (!dev || !dev->enabled) { |
| 339 | printk(BIOS_DEBUG, "Disabling Device 4.\n"); |
| 340 | reg &= ~DEVEN_D4EN; |
| 341 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 342 | dev = pcidev_on_root(6, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 343 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 344 | printk(BIOS_DEBUG, "Disabling PEG60.\n"); |
| 345 | reg &= ~DEVEN_PEG60; |
| 346 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 347 | dev = pcidev_on_root(7, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 348 | if (!dev || !dev->enabled) { |
| 349 | printk(BIOS_DEBUG, "Disabling Device 7.\n"); |
| 350 | reg &= ~DEVEN_D7EN; |
| 351 | } |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 352 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 353 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 354 | pci_write_config32(dev, DEVEN, reg); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 355 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 356 | if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 357 | /* |
| 358 | * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. |
| 359 | * |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 360 | * FIXME: Never clock gate on Ivy Bridge stepping A0! |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 361 | */ |
| 362 | MCHBAR32_OR(PEGCTL, 1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 363 | printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 364 | } else { |
| 365 | MCHBAR32_AND(PEGCTL, ~1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 366 | } |
| 367 | } |
| 368 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 369 | static void northbridge_init(struct device *dev) |
| 370 | { |
| 371 | u8 bios_reset_cpl; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 372 | u32 bridge_type; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 373 | |
| 374 | northbridge_dmi_init(dev); |
| 375 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 376 | bridge_type = MCHBAR32(SAPMTIMERS); |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 377 | bridge_type &= ~0xff; |
| 378 | |
| 379 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 380 | /* Enable Power Aware Interrupt Routing */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 381 | u8 pair = MCHBAR8(INTRDIRCTL); |
| 382 | pair &= ~0x0f; /* Clear 3:0 */ |
| 383 | pair |= 0x04; /* Fixed Priority */ |
| 384 | MCHBAR8(INTRDIRCTL) = pair; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 385 | |
| 386 | /* 30h for IvyBridge */ |
| 387 | bridge_type |= 0x30; |
| 388 | } else { |
| 389 | /* 20h for Sandybridge */ |
| 390 | bridge_type |= 0x20; |
| 391 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 392 | MCHBAR32(SAPMTIMERS) = bridge_type; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 393 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 394 | /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */ |
Patrick Rudolph | aad34cd | 2015-10-21 18:05:01 +0200 | [diff] [blame] | 395 | disable_peg(); |
| 396 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 397 | /* |
| 398 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 399 | * that BIOS has initialized memory and power management |
| 400 | */ |
| 401 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 402 | bios_reset_cpl |= 1; |
| 403 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 404 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 405 | |
| 406 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 407 | mdelay(1); |
| 408 | set_power_limits(28); |
| 409 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 410 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 411 | * CPUs with configurable TDP also need power limits set in MCHBAR. |
| 412 | * Use the same values from MSR_PKG_POWER_LIMIT. |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 413 | */ |
| 414 | if (cpu_config_tdp_levels()) { |
| 415 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 416 | MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = msr.lo; |
| 417 | MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = msr.hi; |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 418 | } |
| 419 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 420 | /* Set here before graphics PM init */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 421 | MCHBAR32(PAVP_MSG) = 0x00100001; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 422 | } |
| 423 | |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 424 | void northbridge_write_smram(u8 smram) |
| 425 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 426 | pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 427 | } |
| 428 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 429 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 430 | .read_resources = mc_read_resources, |
| 431 | .set_resources = pci_dev_set_resources, |
| 432 | .enable_resources = pci_dev_enable_resources, |
| 433 | .init = northbridge_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 434 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 435 | .acpi_fill_ssdt = generate_cpu_entries, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 436 | }; |
| 437 | |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 438 | static const unsigned short pci_device_ids[] = { |
Jonathan A. Kollasch | d346a19 | 2020-02-11 09:03:48 -0600 | [diff] [blame] | 439 | 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 440 | 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ |
| 441 | 0 |
Walter Murphy | 496f4a0 | 2012-04-23 11:08:03 -0700 | [diff] [blame] | 442 | }; |
| 443 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 444 | static const struct pci_driver mc_driver __pci_driver = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 445 | .ops = &mc_ops, |
| 446 | .vendor = PCI_VENDOR_ID_INTEL, |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 447 | .devices = pci_device_ids, |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 448 | }; |
| 449 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 450 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 451 | .read_resources = noop_read_resources, |
| 452 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 453 | .init = mp_cpu_bus_init, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 454 | }; |
| 455 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 456 | static void enable_dev(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 457 | { |
| 458 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 459 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 460 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 461 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 462 | dev->ops = &cpu_bus_ops; |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | struct chip_operations northbridge_intel_sandybridge_ops = { |
Damien Zammit | 3517038 | 2014-10-29 00:11:53 +1100 | [diff] [blame] | 467 | CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 468 | .enable_dev = enable_dev, |
| 469 | }; |