jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <assert.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <stdint.h> |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 24 | #include <string.h> |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 25 | #include <console/console.h> |
| 26 | #include <delay.h> |
| 27 | #include "clock.h" |
| 28 | #include "grf.h" |
| 29 | #include "addressmap.h" |
huang lin | 82ba4d0 | 2014-08-16 10:49:32 +0800 | [diff] [blame] | 30 | #include "soc.h" |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 31 | |
| 32 | struct pll_div { |
| 33 | u32 nr; |
| 34 | u32 nf; |
| 35 | u32 no; |
| 36 | }; |
| 37 | |
| 38 | struct rk3288_cru_reg { |
| 39 | u32 cru_apll_con[4]; |
| 40 | u32 cru_dpll_con[4]; |
| 41 | u32 cru_cpll_con[4]; |
| 42 | u32 cru_gpll_con[4]; |
| 43 | u32 cru_npll_con[4]; |
| 44 | u32 cru_mode_con; |
| 45 | u32 reserved0[3]; |
| 46 | u32 cru_clksel_con[43]; |
| 47 | u32 reserved1[21]; |
| 48 | u32 cru_clkgate_con[19]; |
| 49 | u32 reserved2; |
| 50 | u32 cru_glb_srst_fst_value; |
| 51 | u32 cru_glb_srst_snd_value; |
| 52 | u32 cru_softrst_con[12]; |
| 53 | u32 cru_misc_con; |
| 54 | u32 cru_glb_cnt_th; |
| 55 | u32 cru_glb_rst_con; |
| 56 | u32 reserved3; |
| 57 | u32 cru_glb_rst_st; |
| 58 | u32 reserved4; |
| 59 | u32 cru_sdmmc_con[2]; |
| 60 | u32 cru_sdio0_con[2]; |
| 61 | u32 cru_sdio1_con[2]; |
| 62 | u32 cru_emmc_con[2]; |
| 63 | }; |
| 64 | check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); |
| 65 | |
| 66 | static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; |
| 67 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 68 | #define PLL_DIVISORS(hz, _nr, _no) {\ |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 69 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ |
| 70 | _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ |
| 71 | (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ |
| 72 | "divisors on line " STRINGIFY(__LINE__)); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 73 | |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 74 | /* Keep divisors as low as possible to reduce jitter and power usage. */ |
| 75 | static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); |
| 76 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); |
| 77 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 78 | |
| 79 | /*******************PLL CON0 BITS***************************/ |
| 80 | #define PLL_OD_MSK (0x0F) |
| 81 | |
| 82 | #define PLL_NR_MSK (0x3F << 8) |
| 83 | #define PLL_NR_SHIFT (8) |
| 84 | |
| 85 | /*******************PLL CON1 BITS***************************/ |
| 86 | #define PLL_NF_MSK (0x1FFF) |
| 87 | |
| 88 | /*******************PLL CON2 BITS***************************/ |
| 89 | #define PLL_BWADJ_MSK (0x0FFF) |
| 90 | |
| 91 | /*******************PLL CON3 BITS***************************/ |
| 92 | #define PLL_RESET_MSK (1 << 5) |
| 93 | #define PLL_RESET (1 << 5) |
| 94 | #define PLL_RESET_RESUME (0 << 5) |
| 95 | |
| 96 | /*******************CLKSEL0 BITS***************************/ |
| 97 | /* core clk pll sel: amr or general */ |
| 98 | #define CORE_SEL_PLL_MSK (1 << 15) |
| 99 | #define CORE_SEL_APLL (0 << 15) |
| 100 | #define CORE_SEL_GPLL (1 << 15) |
| 101 | |
| 102 | /* a12 core clock div: clk_core = clk_src / (div_con + 1) */ |
| 103 | #define A12_DIV_SHIFT (8) |
| 104 | #define A12_DIV_MSK (0x1F << 8) |
| 105 | |
| 106 | /* mp core axi clock div: clk = clk_src / (div_con + 1) */ |
| 107 | #define MP_DIV_SHIFT (4) |
| 108 | #define MP_DIV_MSK (0xF << 4) |
| 109 | |
| 110 | /* m0 core axi clock div: clk = clk_src / (div_con + 1) */ |
| 111 | #define M0_DIV_MSK (0xF) |
| 112 | |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 113 | /*******************CLKSEL1 BITS***************************/ |
| 114 | /* pd bus clk pll sel: codec or general */ |
| 115 | #define PD_BUS_SEL_PLL_MSK (1 << 15) |
| 116 | #define PD_BUS_SEL_CPLL (0 << 15) |
| 117 | #define PD_BUS_SEL_GPLL (1 << 15) |
| 118 | |
| 119 | /* pd bus pclk div: |
| 120 | * pclk = pd_bus_aclk /(div + 1) |
| 121 | */ |
| 122 | #define PD_BUS_PCLK_DIV_SHIFT (12) |
| 123 | #define PD_BUS_PCLK_DIV_MSK (0x7 << 12) |
| 124 | |
| 125 | /* pd bus hclk div: |
| 126 | * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 |
| 127 | */ |
| 128 | #define PD_BUS_HCLK_DIV_SHIFT (8) |
| 129 | #define PD_BUS_HCLK_DIV_MSK (0x3 << 8) |
| 130 | |
| 131 | /* pd bus aclk div: |
| 132 | * pd_bus_aclk = pd_bus_src_clk /(div0 * div1) |
| 133 | */ |
| 134 | #define PD_BUS_ACLK_DIV0_SHIFT (3) |
| 135 | #define PD_BUS_ACLK_DIV0_MASK (0x1f << 3) |
| 136 | #define PD_BUS_ACLK_DIV1_SHIFT (0) |
| 137 | #define PD_BUS_ACLK_DIV1_MASK (0x7 << 0) |
| 138 | |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 139 | /*******************CLKSEL10 BITS***************************/ |
| 140 | /* peripheral bus clk pll sel: codec or general */ |
| 141 | #define PERI_SEL_PLL_MSK (1 << 15) |
| 142 | #define PERI_SEL_CPLL (0 << 15) |
| 143 | #define PERI_SEL_GPLL (1 << 15) |
| 144 | |
| 145 | /* peripheral bus pclk div: |
| 146 | * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 |
| 147 | */ |
| 148 | #define PERI_PCLK_DIV_SHIFT (12) |
| 149 | #define PERI_PCLK_DIV_MSK (0x7 << 12) |
| 150 | |
| 151 | /* peripheral bus hclk div: |
| 152 | * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 |
| 153 | */ |
| 154 | #define PERI_HCLK_DIV_SHIFT (8) |
| 155 | #define PERI_HCLK_DIV_MSK (0x3 << 8) |
| 156 | |
| 157 | /* peripheral bus aclk div: |
| 158 | * aclk_periph = |
| 159 | * periph_clk_src / (peri_aclk_div_con + 1) |
| 160 | */ |
huang lin | bbcffd9 | 2014-09-27 12:02:27 +0800 | [diff] [blame] | 161 | #define PERI_ACLK_DIV_SHIFT (0x0) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 162 | #define PERI_ACLK_DIV_MSK (0x1F) |
| 163 | |
| 164 | /*******************CLKSEL37 BITS***************************/ |
| 165 | #define L2_DIV_MSK (0x7) |
| 166 | |
| 167 | #define ATCLK_DIV_MSK (0x1F << 4) |
| 168 | #define ATCLK_DIV_SHIFT (4) |
| 169 | |
| 170 | #define PCLK_DBG_DIV_MSK (0x1F << 9) |
| 171 | #define PCLK_DBG_DIV_SHIFT (9) |
| 172 | |
| 173 | #define APLL_MODE_MSK (0x3) |
| 174 | #define APLL_MODE_SLOW (0) |
| 175 | #define APLL_MODE_NORM (1) |
| 176 | |
| 177 | #define DPLL_MODE_MSK (0x3 << 4) |
| 178 | #define DPLL_MODE_SLOW (0 << 4) |
| 179 | #define DPLL_MODE_NORM (1 << 4) |
| 180 | |
| 181 | #define CPLL_MODE_MSK (0x3 << 8) |
| 182 | #define CPLL_MODE_SLOW (0 << 8) |
| 183 | #define CPLL_MODE_NORM (1 << 8) |
| 184 | |
| 185 | #define GPLL_MODE_MSK (0x3 << 12) |
| 186 | #define GPLL_MODE_SLOW (0 << 12) |
| 187 | #define GPLL_MODE_NORM (1 << 12) |
| 188 | |
| 189 | #define SOCSTS_DPLL_LOCK (1 << 5) |
| 190 | #define SOCSTS_APLL_LOCK (1 << 6) |
| 191 | #define SOCSTS_CPLL_LOCK (1 << 7) |
| 192 | #define SOCSTS_GPLL_LOCK (1 << 8) |
| 193 | |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 194 | static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 195 | { |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 196 | /* All PLLs have same VCO and output frequency range restrictions. */ |
| 197 | u32 vco_khz = OSC_HZ/KHz * div->nf / div->nr; |
| 198 | u32 output_khz = vco_khz / div->no; |
| 199 | |
| 200 | printk(BIOS_DEBUG, "Configuring PLL at %p with NF = %d, NR = %d and " |
| 201 | "NO = %d (VCO = %uKHz, output = %uKHz)\n", |
| 202 | pll_con, div->nf, div->nr, div->no, vco_khz, output_khz); |
| 203 | assert(vco_khz >= 440*(MHz/KHz) && vco_khz <= 2200*(MHz/KHz) && |
| 204 | output_khz >= 27500 && output_khz <= 2200*(MHz/KHz) && |
| 205 | (div->no == 1 || !(div->no % 2))); |
| 206 | |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 207 | /* enter rest */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 208 | writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 209 | |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 210 | writel(RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) |
| 211 | | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)), &pll_con[0]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 212 | |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 213 | writel(RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)), &pll_con[1]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 214 | |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 215 | writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)), &pll_con[2]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 216 | |
| 217 | udelay(10); |
| 218 | |
| 219 | /* return form rest */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 220 | writel(RK_CLRBITS(PLL_RESET_MSK), &pll_con[3]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 221 | |
| 222 | return 0; |
| 223 | } |
| 224 | |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 225 | /* |
| 226 | TODO: |
| 227 | it should be replaced by lib.h function |
| 228 | 'unsigned long log2(unsigned long x)' |
| 229 | */ |
| 230 | static unsigned int log2(unsigned int value) |
| 231 | { |
| 232 | unsigned int div = 0; |
| 233 | |
| 234 | while (value != 1) { |
| 235 | div++; |
| 236 | value = ALIGN_UP(value, 2) / 2; |
| 237 | } |
| 238 | return div; |
| 239 | } |
| 240 | |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 241 | void rkclk_init(void) |
| 242 | { |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 243 | u32 aclk_div; |
| 244 | u32 hclk_div; |
| 245 | u32 pclk_div; |
| 246 | |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 247 | /* pll enter slow-mode */ |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 248 | writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 249 | | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 250 | &cru_ptr->cru_mode_con); |
| 251 | |
| 252 | /* init pll */ |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 253 | rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg); |
| 254 | rkclk_set_pll(&cru_ptr->cru_cpll_con[0], &cpll_init_cfg); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 255 | |
| 256 | /* waiting for pll lock */ |
| 257 | while (1) { |
| 258 | if ((readl(&rk3288_grf->soc_status[1]) |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 259 | & (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) |
| 260 | == (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 261 | break; |
| 262 | udelay(1); |
| 263 | } |
| 264 | |
| 265 | /* |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 266 | * pd_bus clock pll source selection and |
| 267 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. |
| 268 | */ |
| 269 | aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; |
| 270 | assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
| 271 | hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; |
| 272 | assert((hclk_div + 1) * PD_BUS_HCLK_HZ == |
| 273 | PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); |
| 274 | |
| 275 | pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; |
| 276 | assert((pclk_div + 1) * PD_BUS_PCLK_HZ == |
| 277 | PD_BUS_ACLK_HZ && pclk_div < 0x7); |
| 278 | |
| 279 | writel(RK_SETBITS(PD_BUS_SEL_GPLL) |
| 280 | | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, |
| 281 | pclk_div << PD_BUS_PCLK_DIV_SHIFT) |
| 282 | | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, |
| 283 | hclk_div << PD_BUS_HCLK_DIV_SHIFT) |
| 284 | | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, |
| 285 | aclk_div << PD_BUS_ACLK_DIV0_SHIFT) |
| 286 | | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0), |
| 287 | &cru_ptr->cru_clksel_con[1]); |
| 288 | |
| 289 | /* |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 290 | * peri clock pll source selection and |
| 291 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 292 | */ |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 293 | aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; |
| 294 | assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
| 295 | |
| 296 | hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); |
| 297 | assert((1 << hclk_div) * PERI_HCLK_HZ == |
| 298 | PERI_ACLK_HZ && (hclk_div < 0x4)); |
| 299 | |
| 300 | pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); |
| 301 | assert((1 << pclk_div) * PERI_PCLK_HZ == |
| 302 | PERI_ACLK_HZ && (pclk_div < 0x4)); |
| 303 | |
| 304 | writel(RK_SETBITS(PERI_SEL_GPLL) |
| 305 | | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, |
| 306 | pclk_div << PERI_PCLK_DIV_SHIFT) |
| 307 | | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, |
| 308 | hclk_div << PERI_HCLK_DIV_SHIFT) |
| 309 | | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, |
| 310 | aclk_div << PERI_ACLK_DIV_SHIFT), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 311 | &cru_ptr->cru_clksel_con[10]); |
| 312 | |
| 313 | /* PLL enter normal-mode */ |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 314 | writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 315 | | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 316 | &cru_ptr->cru_mode_con); |
| 317 | |
| 318 | } |
| 319 | |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 320 | void rkclk_configure_cpu() |
| 321 | { |
| 322 | /* pll enter slow-mode */ |
| 323 | writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW), |
| 324 | &cru_ptr->cru_mode_con); |
| 325 | |
| 326 | rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); |
| 327 | |
| 328 | /* waiting for pll lock */ |
| 329 | while (1) { |
| 330 | if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK) |
| 331 | break; |
| 332 | udelay(1); |
| 333 | } |
| 334 | |
| 335 | /* |
| 336 | * core clock pll source selection and |
| 337 | * set up dependent divisors for MPAXI/M0AXI and ARM clocks. |
| 338 | * core clock select apll, apll clk = 1800MHz |
| 339 | * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz |
| 340 | */ |
| 341 | writel(RK_CLRBITS(CORE_SEL_PLL_MSK) |
| 342 | | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) |
| 343 | | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) |
| 344 | | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0), |
| 345 | &cru_ptr->cru_clksel_con[0]); |
| 346 | |
| 347 | /* |
| 348 | * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. |
| 349 | * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz |
| 350 | */ |
| 351 | writel(RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) |
| 352 | | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) |
| 353 | | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)), |
| 354 | &cru_ptr->cru_clksel_con[37]); |
| 355 | |
| 356 | /* PLL enter normal-mode */ |
| 357 | writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM), |
| 358 | &cru_ptr->cru_mode_con); |
| 359 | } |
| 360 | |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 361 | void rkclk_configure_ddr(unsigned int hz) |
| 362 | { |
| 363 | struct pll_div dpll_cfg; |
| 364 | |
Julius Werner | f8dcdea | 2014-10-06 15:02:12 -0700 | [diff] [blame^] | 365 | switch (hz) { |
| 366 | case 300*MHz: |
| 367 | dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1}; |
| 368 | break; |
| 369 | case 533*MHz: /* actually 533.3P MHz */ |
| 370 | dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2}; |
| 371 | break; |
| 372 | case 666*MHz: /* actually 666.6P MHz */ |
| 373 | dpll_cfg = (struct pll_div){.nf = 500, .nr = 9, .no = 2}; |
| 374 | break; |
| 375 | case 800*MHz: |
| 376 | dpll_cfg = (struct pll_div){.nf = 100, .nr = 3, .no = 1}; |
| 377 | break; |
| 378 | default: |
| 379 | die("Unsupported SDRAM frequency, add to clock.c!"); |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 380 | } |
| 381 | |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 382 | /* pll enter slow-mode */ |
| 383 | writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), |
| 384 | &cru_ptr->cru_mode_con); |
| 385 | |
| 386 | rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg); |
| 387 | |
| 388 | /* waiting for pll lock */ |
| 389 | while (1) { |
| 390 | if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK) |
| 391 | break; |
| 392 | udelay(1); |
| 393 | } |
| 394 | |
| 395 | /* PLL enter normal-mode */ |
| 396 | writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM), |
| 397 | &cru_ptr->cru_mode_con); |
| 398 | } |
| 399 | |
| 400 | void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) |
| 401 | { |
| 402 | u32 phy_ctl_srstn_shift = 4 + 5 * ch; |
| 403 | u32 ctl_psrstn_shift = 3 + 5 * ch; |
| 404 | u32 ctl_srstn_shift = 2 + 5 * ch; |
| 405 | u32 phy_psrstn_shift = 1 + 5 * ch; |
| 406 | u32 phy_srstn_shift = 5 * ch; |
| 407 | |
| 408 | writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, |
| 409 | phy << phy_ctl_srstn_shift) |
| 410 | | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) |
| 411 | | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) |
| 412 | | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) |
| 413 | | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift), |
| 414 | &cru_ptr->cru_softrst_con[10]); |
| 415 | } |
| 416 | |
| 417 | void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n) |
| 418 | { |
| 419 | u32 phy_ctl_srstn_shift = 4 + 5 * ch; |
| 420 | |
| 421 | writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, |
| 422 | n << phy_ctl_srstn_shift), |
| 423 | &cru_ptr->cru_softrst_con[10]); |
| 424 | } |
| 425 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 426 | void rkclk_configure_spi(unsigned int bus, unsigned int hz) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 427 | { |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 428 | int src_clk_div = GPLL_HZ / hz; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 429 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 430 | assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ)); |
| 431 | |
| 432 | switch (bus) { /*select gpll as spi src clk, and set div*/ |
| 433 | case 0: |
| 434 | writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 |
| 435 | | (src_clk_div - 1) << 0), |
| 436 | &cru_ptr->cru_clksel_con[25]); |
| 437 | break; |
| 438 | case 1: |
| 439 | writel(RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 |
| 440 | | (src_clk_div - 1) << 8), |
| 441 | &cru_ptr->cru_clksel_con[25]); |
| 442 | break; |
| 443 | case 2: |
| 444 | writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 |
| 445 | | (src_clk_div - 1) << 0), |
| 446 | &cru_ptr->cru_clksel_con[39]); |
| 447 | break; |
| 448 | default: |
| 449 | printk(BIOS_ERR, "do not support this spi bus\n"); |
| 450 | } |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 451 | } |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 452 | |
| 453 | static u32 clk_gcd(u32 a, u32 b) |
| 454 | { |
| 455 | while (b != 0) { |
| 456 | int r = b; |
| 457 | b = a % b; |
| 458 | a = r; |
| 459 | } |
| 460 | return a; |
| 461 | } |
| 462 | |
| 463 | void rkclk_configure_i2s(unsigned int hz) |
| 464 | { |
| 465 | int n, d; |
| 466 | int v; |
| 467 | |
| 468 | /* i2s source clock: gpll |
| 469 | i2s0_outclk_sel: clk_i2s |
| 470 | i2s0_clk_sel: divider ouput from fraction |
| 471 | i2s0_pll_div_con: 0*/ |
| 472 | writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 , |
| 473 | 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0), |
| 474 | &cru_ptr->cru_clksel_con[4]); |
| 475 | |
| 476 | /* set frac divider */ |
| 477 | v = clk_gcd(GPLL_HZ, hz); |
| 478 | n = (GPLL_HZ / v) & (0xffff); |
| 479 | d = (hz / v) & (0xffff); |
| 480 | assert(hz == GPLL_HZ / n * d); |
| 481 | writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); |
| 482 | } |