jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <assert.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <stdint.h> |
| 24 | #include <console/console.h> |
| 25 | #include <delay.h> |
| 26 | #include "clock.h" |
| 27 | #include "grf.h" |
| 28 | #include "addressmap.h" |
huang lin | 82ba4d0 | 2014-08-16 10:49:32 +0800 | [diff] [blame] | 29 | #include "soc.h" |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 30 | |
| 31 | struct pll_div { |
| 32 | u32 nr; |
| 33 | u32 nf; |
| 34 | u32 no; |
| 35 | }; |
| 36 | |
| 37 | struct rk3288_cru_reg { |
| 38 | u32 cru_apll_con[4]; |
| 39 | u32 cru_dpll_con[4]; |
| 40 | u32 cru_cpll_con[4]; |
| 41 | u32 cru_gpll_con[4]; |
| 42 | u32 cru_npll_con[4]; |
| 43 | u32 cru_mode_con; |
| 44 | u32 reserved0[3]; |
| 45 | u32 cru_clksel_con[43]; |
| 46 | u32 reserved1[21]; |
| 47 | u32 cru_clkgate_con[19]; |
| 48 | u32 reserved2; |
| 49 | u32 cru_glb_srst_fst_value; |
| 50 | u32 cru_glb_srst_snd_value; |
| 51 | u32 cru_softrst_con[12]; |
| 52 | u32 cru_misc_con; |
| 53 | u32 cru_glb_cnt_th; |
| 54 | u32 cru_glb_rst_con; |
| 55 | u32 reserved3; |
| 56 | u32 cru_glb_rst_st; |
| 57 | u32 reserved4; |
| 58 | u32 cru_sdmmc_con[2]; |
| 59 | u32 cru_sdio0_con[2]; |
| 60 | u32 cru_sdio1_con[2]; |
| 61 | u32 cru_emmc_con[2]; |
| 62 | }; |
| 63 | check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); |
| 64 | |
| 65 | static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; |
| 66 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 67 | #define PLL_DIVISORS(hz, _nr, _no) {\ |
| 68 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / 24000000), .no = _no};\ |
| 69 | _Static_assert(((u64)hz * _nr * _no / 24000000) * 24000000 /\ |
| 70 | (_nr * _no) == hz,\ |
| 71 | #hz "Hz cannot be hit with PLL divisors in " __FILE__); |
| 72 | |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 73 | /* apll = 816MHz, gpll = 594MHz, cpll = 384MHz */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 74 | static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 2); |
| 75 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 4); |
| 76 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 77 | |
| 78 | /*******************PLL CON0 BITS***************************/ |
| 79 | #define PLL_OD_MSK (0x0F) |
| 80 | |
| 81 | #define PLL_NR_MSK (0x3F << 8) |
| 82 | #define PLL_NR_SHIFT (8) |
| 83 | |
| 84 | /*******************PLL CON1 BITS***************************/ |
| 85 | #define PLL_NF_MSK (0x1FFF) |
| 86 | |
| 87 | /*******************PLL CON2 BITS***************************/ |
| 88 | #define PLL_BWADJ_MSK (0x0FFF) |
| 89 | |
| 90 | /*******************PLL CON3 BITS***************************/ |
| 91 | #define PLL_RESET_MSK (1 << 5) |
| 92 | #define PLL_RESET (1 << 5) |
| 93 | #define PLL_RESET_RESUME (0 << 5) |
| 94 | |
| 95 | /*******************CLKSEL0 BITS***************************/ |
| 96 | /* core clk pll sel: amr or general */ |
| 97 | #define CORE_SEL_PLL_MSK (1 << 15) |
| 98 | #define CORE_SEL_APLL (0 << 15) |
| 99 | #define CORE_SEL_GPLL (1 << 15) |
| 100 | |
| 101 | /* a12 core clock div: clk_core = clk_src / (div_con + 1) */ |
| 102 | #define A12_DIV_SHIFT (8) |
| 103 | #define A12_DIV_MSK (0x1F << 8) |
| 104 | |
| 105 | /* mp core axi clock div: clk = clk_src / (div_con + 1) */ |
| 106 | #define MP_DIV_SHIFT (4) |
| 107 | #define MP_DIV_MSK (0xF << 4) |
| 108 | |
| 109 | /* m0 core axi clock div: clk = clk_src / (div_con + 1) */ |
| 110 | #define M0_DIV_MSK (0xF) |
| 111 | |
| 112 | /*******************CLKSEL10 BITS***************************/ |
| 113 | /* peripheral bus clk pll sel: codec or general */ |
| 114 | #define PERI_SEL_PLL_MSK (1 << 15) |
| 115 | #define PERI_SEL_CPLL (0 << 15) |
| 116 | #define PERI_SEL_GPLL (1 << 15) |
| 117 | |
| 118 | /* peripheral bus pclk div: |
| 119 | * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 |
| 120 | */ |
| 121 | #define PERI_PCLK_DIV_SHIFT (12) |
| 122 | #define PERI_PCLK_DIV_MSK (0x7 << 12) |
| 123 | |
| 124 | /* peripheral bus hclk div: |
| 125 | * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 |
| 126 | */ |
| 127 | #define PERI_HCLK_DIV_SHIFT (8) |
| 128 | #define PERI_HCLK_DIV_MSK (0x3 << 8) |
| 129 | |
| 130 | /* peripheral bus aclk div: |
| 131 | * aclk_periph = |
| 132 | * periph_clk_src / (peri_aclk_div_con + 1) |
| 133 | */ |
| 134 | #define PERI_ACLK_DIV_MSK (0x1F) |
| 135 | |
| 136 | /*******************CLKSEL37 BITS***************************/ |
| 137 | #define L2_DIV_MSK (0x7) |
| 138 | |
| 139 | #define ATCLK_DIV_MSK (0x1F << 4) |
| 140 | #define ATCLK_DIV_SHIFT (4) |
| 141 | |
| 142 | #define PCLK_DBG_DIV_MSK (0x1F << 9) |
| 143 | #define PCLK_DBG_DIV_SHIFT (9) |
| 144 | |
| 145 | #define APLL_MODE_MSK (0x3) |
| 146 | #define APLL_MODE_SLOW (0) |
| 147 | #define APLL_MODE_NORM (1) |
| 148 | |
| 149 | #define DPLL_MODE_MSK (0x3 << 4) |
| 150 | #define DPLL_MODE_SLOW (0 << 4) |
| 151 | #define DPLL_MODE_NORM (1 << 4) |
| 152 | |
| 153 | #define CPLL_MODE_MSK (0x3 << 8) |
| 154 | #define CPLL_MODE_SLOW (0 << 8) |
| 155 | #define CPLL_MODE_NORM (1 << 8) |
| 156 | |
| 157 | #define GPLL_MODE_MSK (0x3 << 12) |
| 158 | #define GPLL_MODE_SLOW (0 << 12) |
| 159 | #define GPLL_MODE_NORM (1 << 12) |
| 160 | |
| 161 | #define SOCSTS_DPLL_LOCK (1 << 5) |
| 162 | #define SOCSTS_APLL_LOCK (1 << 6) |
| 163 | #define SOCSTS_CPLL_LOCK (1 << 7) |
| 164 | #define SOCSTS_GPLL_LOCK (1 << 8) |
| 165 | |
| 166 | static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg) |
| 167 | { |
| 168 | /* enter rest */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 169 | writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 170 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 171 | writel(RK_CLRSETBITS(PLL_NR_MSK, (pll_div_cfg->nr - 1) << PLL_NR_SHIFT) |
| 172 | | RK_CLRSETBITS(PLL_OD_MSK, (pll_div_cfg->no - 1)), &pll_con[0]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 173 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 174 | writel(RK_CLRSETBITS(PLL_NF_MSK, (pll_div_cfg->nf - 1)), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 175 | &pll_con[1]); |
| 176 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 177 | writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((pll_div_cfg->nf >> 1) - 1)), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 178 | &pll_con[2]); |
| 179 | |
| 180 | udelay(10); |
| 181 | |
| 182 | /* return form rest */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 183 | writel(RK_CLRBITS(PLL_RESET_MSK), &pll_con[3]); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | void rkclk_init(void) |
| 189 | { |
| 190 | /* pll enter slow-mode */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 191 | writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW) |
| 192 | | RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 193 | | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 194 | &cru_ptr->cru_mode_con); |
| 195 | |
| 196 | /* init pll */ |
| 197 | rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); |
| 198 | rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg); |
| 199 | rkclk_set_pll(&cru_ptr->cru_cpll_con[0], &cpll_init_cfg); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 200 | |
| 201 | /* waiting for pll lock */ |
| 202 | while (1) { |
| 203 | if ((readl(&rk3288_grf->soc_status[1]) |
| 204 | & (SOCSTS_APLL_LOCK | SOCSTS_CPLL_LOCK |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 205 | | SOCSTS_GPLL_LOCK)) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 206 | == (SOCSTS_APLL_LOCK | SOCSTS_CPLL_LOCK |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 207 | | SOCSTS_GPLL_LOCK)) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 208 | break; |
| 209 | udelay(1); |
| 210 | } |
| 211 | |
| 212 | /* |
| 213 | * core clock pll source selection and |
| 214 | * set up dependent divisors for MPAXI/M0AXI and ARM clocks. |
| 215 | * core clock select apll, apll clk = 816MHz |
| 216 | * arm clk = 816MHz, mpclk = 204MHz, m0clk = 408MHz |
| 217 | */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 218 | writel(RK_CLRBITS(CORE_SEL_PLL_MSK) |
| 219 | | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) |
| 220 | | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) |
| 221 | | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 222 | &cru_ptr->cru_clksel_con[0]); |
| 223 | |
| 224 | /* |
| 225 | * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. |
| 226 | * l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz |
| 227 | */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 228 | writel(RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) |
| 229 | | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) |
| 230 | | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 231 | &cru_ptr->cru_clksel_con[37]); |
| 232 | |
| 233 | /* |
| 234 | * peri clock pll source selection and |
| 235 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. |
| 236 | * peri clock select gpll, gpll clk = 594MHz |
| 237 | * aclk = 148.5MHz, hclk = 148.5Mhz, pclk = 74.25MHz |
| 238 | */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 239 | writel(RK_SETBITS(PERI_SEL_PLL_MSK) |
| 240 | | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, 1 << PERI_PCLK_DIV_SHIFT) |
| 241 | | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, 0 << PERI_HCLK_DIV_SHIFT) |
| 242 | | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, 3 << 0), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 243 | &cru_ptr->cru_clksel_con[10]); |
| 244 | |
| 245 | /* PLL enter normal-mode */ |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 246 | writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM) |
| 247 | | RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 248 | | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM), |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 249 | &cru_ptr->cru_mode_con); |
| 250 | |
| 251 | } |
| 252 | |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 253 | void rkclk_configure_ddr(unsigned int hz) |
| 254 | { |
| 255 | struct pll_div dpll_cfg; |
| 256 | |
| 257 | if (hz <= 150000000) { |
| 258 | dpll_cfg.nr = 3; |
| 259 | dpll_cfg.no = 8; |
| 260 | } else if (hz <= 540000000) { |
| 261 | dpll_cfg.nr = 6; |
| 262 | dpll_cfg.no = 4; |
| 263 | } else { |
| 264 | dpll_cfg.nr = 1; |
| 265 | dpll_cfg.no = 1; |
| 266 | } |
| 267 | |
| 268 | dpll_cfg.nf = (hz / 1000 * dpll_cfg.nr * dpll_cfg.no) / 24000; |
| 269 | assert(dpll_cfg.nf < 4096 |
| 270 | && hz == dpll_cfg.nf * 24000 / (dpll_cfg.nr * dpll_cfg.no) |
| 271 | * 1000); |
| 272 | /* pll enter slow-mode */ |
| 273 | writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), |
| 274 | &cru_ptr->cru_mode_con); |
| 275 | |
| 276 | rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg); |
| 277 | |
| 278 | /* waiting for pll lock */ |
| 279 | while (1) { |
| 280 | if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK) |
| 281 | break; |
| 282 | udelay(1); |
| 283 | } |
| 284 | |
| 285 | /* PLL enter normal-mode */ |
| 286 | writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM), |
| 287 | &cru_ptr->cru_mode_con); |
| 288 | } |
| 289 | |
| 290 | void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) |
| 291 | { |
| 292 | u32 phy_ctl_srstn_shift = 4 + 5 * ch; |
| 293 | u32 ctl_psrstn_shift = 3 + 5 * ch; |
| 294 | u32 ctl_srstn_shift = 2 + 5 * ch; |
| 295 | u32 phy_psrstn_shift = 1 + 5 * ch; |
| 296 | u32 phy_srstn_shift = 5 * ch; |
| 297 | |
| 298 | writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, |
| 299 | phy << phy_ctl_srstn_shift) |
| 300 | | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) |
| 301 | | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) |
| 302 | | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) |
| 303 | | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift), |
| 304 | &cru_ptr->cru_softrst_con[10]); |
| 305 | } |
| 306 | |
| 307 | void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n) |
| 308 | { |
| 309 | u32 phy_ctl_srstn_shift = 4 + 5 * ch; |
| 310 | |
| 311 | writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, |
| 312 | n << phy_ctl_srstn_shift), |
| 313 | &cru_ptr->cru_softrst_con[10]); |
| 314 | } |
| 315 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 316 | void rkclk_configure_spi(unsigned int bus, unsigned int hz) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 317 | { |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 318 | int src_clk_div = GPLL_HZ / hz; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 319 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 320 | assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ)); |
| 321 | |
| 322 | switch (bus) { /*select gpll as spi src clk, and set div*/ |
| 323 | case 0: |
| 324 | writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 |
| 325 | | (src_clk_div - 1) << 0), |
| 326 | &cru_ptr->cru_clksel_con[25]); |
| 327 | break; |
| 328 | case 1: |
| 329 | writel(RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 |
| 330 | | (src_clk_div - 1) << 8), |
| 331 | &cru_ptr->cru_clksel_con[25]); |
| 332 | break; |
| 333 | case 2: |
| 334 | writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 |
| 335 | | (src_clk_div - 1) << 0), |
| 336 | &cru_ptr->cru_clksel_con[39]); |
| 337 | break; |
| 338 | default: |
| 339 | printk(BIOS_ERR, "do not support this spi bus\n"); |
| 340 | } |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 341 | } |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame^] | 342 | |
| 343 | static u32 clk_gcd(u32 a, u32 b) |
| 344 | { |
| 345 | while (b != 0) { |
| 346 | int r = b; |
| 347 | b = a % b; |
| 348 | a = r; |
| 349 | } |
| 350 | return a; |
| 351 | } |
| 352 | |
| 353 | void rkclk_configure_i2s(unsigned int hz) |
| 354 | { |
| 355 | int n, d; |
| 356 | int v; |
| 357 | |
| 358 | /* i2s source clock: gpll |
| 359 | i2s0_outclk_sel: clk_i2s |
| 360 | i2s0_clk_sel: divider ouput from fraction |
| 361 | i2s0_pll_div_con: 0*/ |
| 362 | writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 , |
| 363 | 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0), |
| 364 | &cru_ptr->cru_clksel_con[4]); |
| 365 | |
| 366 | /* set frac divider */ |
| 367 | v = clk_gcd(GPLL_HZ, hz); |
| 368 | n = (GPLL_HZ / v) & (0xffff); |
| 369 | d = (hz / v) & (0xffff); |
| 370 | assert(hz == GPLL_HZ / n * d); |
| 371 | writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); |
| 372 | } |